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Summary of Contents for JYTEK NuDAQ PCI-69222
- Page 1 ® NuDAQ PCI-69222 ® NuDAQ PCI-69223 16-bit High-Performance DAQ Card with Programmable Function I/O User’s Manual Manual Rev. 1.00 Revision Date: May 30, 2017 Advance Technologies; Automate the World.
- Page 2 All specifications are subject to change without further notice. Audience and scope This manual guides you when using JYTEK high-performance data acquisition PCI card. The card’s hardware, signal connec- tions, and calibration information are provided for faster applica- tion building.
- Page 3 Warranty Policy: This presents the JYTEK Warranty Policy terms and coverages. Getting Service: Contact information for JYTEK’s worldwide offices. Conventions Take note of the following conventions used throughout the man- ual to make sure that you perform certain tasks and instructions properly.
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Page 5: Table Of Contents
Table of Contents Table of Contents................i List of Tables .................. iii List of Figures ................. iv 1 Introduction................1 Features ..................2 Applications ................... 2 Specifications ................. 3 Unpacking Checklist ............... 8 Software Support................8 Driver Support for Windows ............9 2 Hardware Information ............ - Page 6 Acquisition Mode (Software Polling) ......30 Continuous Acquisition (Scanning) Mode ......31 Trigger Modes ................ 34 Bus-mastering DMA Data Transfer ........36 D/A Conversion ................39 Bipolar Output Modes ............39 Software Update ..............39 Waveform Generation ............39 Programmable Function I/O............48 TTL DI/DO ................
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Page 7: List Of Tables
List of Tables Table 2-1: CN1 Pin Assignment for PCI-69222 ........14 Table 2-2: CN1 Pin Assignment for PCI-69223 ........15 Table 2-3: CN2 Pin Assignment for PCI-69222/PCI-69223 ....16 Table 2-4: CN1/CN2 Signal Description ..........17 Table 2-5: SSI Connector Pin Assignment ......... 18 Table 2-6: SSI Connector Signal Description ........ - Page 8 List of Figures Figure 1-1: JYTEK Software Support Overview ........9 Figure 1-2: DAQPilot Main Interface........... 10 Figure 1-3: DAQMaster Device Manager..........10 Figure 1-4: Legacy Software Support Overview........11 Figure 2-1: PCI-69222/PCI-69223 Layout..........13 Figure 2-2: Floating Source and RSE Input Connections..... 21...
- Page 9 Figure 4-29: Digital Waveform Generation Operation ......57 Figure 4-30: Encoder Isolation Input Module ........58 Figure 4-31: Encoder OGRx Input ............59 Figure 4-32: CW/CCW Encoder Timing ..........59 Figure 4-33: X1 Encoder Mode ............. 60 Figure 4-34: X2 Encoder Mode ............. 60 Figure 4-35: X4 Encoder Mode .............
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Page 11: Introduction
Introduction The NuDAQ PCI-69222 (16-CH, 250 kS/s) and NuDAQ PCI- 69223 (32-CH, 500 kS/s) are 16-bit high-performance DAQ cards with eight different input ranges. These cards also features a 2- CH, 16-bit analog output capable of up to 1 MS/s update rate, a 2- CH encoder input, and a programmable function I/O. -
Page 12: Features
Features The PCI-69222/PCI-69223 comes with the following features: Supports a 32-bit 3.3 V or 5 V PCI bus PCI 2.3-compliant Up to 32-CH single-ended or 16-CH differential analog input Up to 500 kS/s sampling rate Programmable analog input gains of 1, 2, 4, 5, 8, 10, 20, 40 ... -
Page 13: Specifications
Specifications Analog Input (AI) Hardware PCI-69222 PCI-69223 Number of channels (programmable) A/D converter AD7685 or equivalent AD7686 or equivalent Maximum sampling rate Single-channel: 250 K samples/s 500 K samples/s Scanning: 100 K samples/s 200 K samples/s Resolution 16-bit Input coupling Programmable input range ±10 V, ±5 V, ±2.5 V, ±2 V, ±1.25 V, ±1 V, ±500 mV, ±250 mV... - Page 14 Spurious-free dynamic range 95 dB 88 dB (SFDR) Signal-to-noise and distortion 86 dB 84 dB ratio (SINAD) Total harmonic distortion –94 dB –90 dB (THD) Signal-to-noise ration (SNR) 87 dB 86 dB Effective number of bits 13.9 13.5 (ENOB) Settling time to full-scale step Multiple channels 2 µs to 0.1% error Multiple ranges...
- Page 15 Fall time 0.7 µs Settling time to 1% output 3 µs error 0.7 LSB 1 LSB Output driving ±5 mA (maximum) Function I/O Number of channels • 16-CH programmable function DI • 16-CH programmable function DO Compatibility TTL (single-ended) (supports 3.3 V and 5 V DI; 3.3 V DO) Input voltage •...
- Page 16 Encoder Input (EI) Number of channels Max. Input frequency 4 MHz Encoder count (2³¹-1) bits Photo isolator NEC PS9115 or equivalent Encoder modes • CW/CCW • X1 AB phase encoder • X2 AB phase encoder • X4 AB phase encoder Physical, Power, and Operating Environment Interface PCI 2.3-compliant...
- Page 17 2. System Noise (LSBrms, including Quantization, Typical, 25 º Input Range System Noise ±10 V 0.78 LSBrms ±5 V 0.80 LSBrms ±2.5 V 0.98 LSBrms ±2 V 0.96 LSBrms ±1.25 V 0.77 LSBrms ±1 V 0.81 LSBrms ±500 mV 0.99 LSBrms ±250 mV 0.96 LSBrms 3.
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Page 18: Unpacking Checklist
Wear a grounded wrist strap when servicing.Software Support Software Support JYTEK provides comprehensive software drivers and packages to suit various user approach to building a system. Aside from pro- gramming libraries, such as DLLs, for most Windows-based sys-... -
Page 19: Driver Support For Windows
Driver Support for Windows DAQPilot DAQPilot is a driver and SDK with a graphics-driven interface for various application development environments. DAQPilot comes as JYTEK's commitment to provide full support to its comprehensive line data acquisition products and designed for the novice to the most experienced programmer. -
Page 20: Figure 1-2: Daqpilot Main Interface
You can download and install DAQPilot at http://www.jytek.com. DAQMaster The JYTEK DAQMaster is a smart device manager that opens up access to JYTEK data acquisition and test and measure- ment products. DAQMaster delivers all-in-one configurations and provides you with a full support matrix to properly and con- veniently configure JYTEK Test and Measurement products. -
Page 21: Figure 1-4: Legacy Software Support Overview
Figure 1-4: Legacy Software Support Overview NOTE JYTEK strongly recommends installing DAQPilot and avoid using legacy DASK drivers. For current DASK driv- er users or those who do not have Internet access, we of- fer an installation CD. Contact your JYTEK distributor for details. Introduction... - Page 22 Digitally-signed for Windows Vista 64-bit edition Utilizes WOW64 subsystem to ensure that 32-bit applications run normally on 64-bit editions of Windows XP, Windows 2003 Server, and Windows Vista without modification For more information about Windows Vista support, visit http://www.jytek.com. Introduction...
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Page 23: Hardware Information
Hardware Information This chapter provides information on the PCI-69222/PCI-69223 layout, connectors, and pin assignments. Card Layout Figure 2-1 shows the PCI-69222/PCI-69223 board layout and dimen- sions. 102.46 70.22 106.4 Figure 2-1: PCI-69222/PCI-69223 Layout Connector Pin Assignment The PCI-69222/PCI-69223 card is equipped with two VHDCI 68- pin connectors. -
Page 24: Cn1 Pin Assignment
CN1 Pin Assignment Definition Pin # Definition AI0(AIH0) AI8(AIL0) AI1(AIH1) AI9(AIL1) AI2(AIH2) AI10(AIL2) AI3(AIH3) AI11(AIL3) AI4(AIH4) AI12(AIL4) AI5(AIH5) AI13(AIL5) AI6(AIH6) AI14(AIL6) AI7(AIH7) AI15(AIL7) AGND AISENSE AGND AGND AGND AGND Table 2-1: CN1 Pin Assignment for PCI-69222 Hardware Information... -
Page 25: Table 2-2: Cn1 Pin Assignment For Pci-69223
Definition Pin # Definition AI0(AIH0) AI16(AIL0) AI1(AIH1) AI17(AIL1) AI2(AIH2) AI18(AIL2) AI3(AIH3) AI19(AIL3) AI4(AIH4) AI20(AIL4) AI5(AIH5) AI21(AIL5) AI6(AIH6) AI22(AIL6) AI7(AIH7) AI23(AIL7) AGND AISENSE AI8(AIH8) AI24(AIL8) AI9(AIH9) AI25(AIL9) AI10(AIH10) AI26(AIL10) AI11(AIH11) AI27(AIL11) AI12(AIH12) AI28(AIL12) AI13(AIH13) AI29(AIL13) AI14(AIH14) AI30(AIL14) AI15(AIH15) AI31(AIL15) AGND AGND AGND AGND Table 2-2: CN1 Pin Assignment for PCI-69223... -
Page 26: Cn2 Pin Assignment
CN2 Pin Assignment Definition Pin # Definition GPI0/GPTC_CLK0 GPI8/GPTC_CLK2 GPI1/GPTC_UD0 GPI9/GPTC_UD2 GPI2/GPTC_GATE0 GPI10/GPTC_GATE2 GPI3/GPTC_AUX0 GPI11/GPTC_AUX2 GPI4/GPTC_CLK1 GPI12/GPTC_CLK3 GPI5/GPTC_UD1 GPI13/GPTC_UD3 GPI6/GPTC_GATE1 GPI14/GPTC_GATE3 GPI7/GPTC_AUX1 GPI15/GPTC_AUX3 DGND DGND GPO0/GPTC_OUT0 GPO8 GPO1/GPTC_OUT1 GPO9 GPO2/GPTC_OUT2 GPO10 GPO3/GPTC_OUT3 GPO11 GPO4 GPO12 GPO5 GPO13 GPO6 GPO14 GPO7 GPO15 DGND DGND... -
Page 27: Cn1/Cn2 Signal Descriptions
CN1/CN2 Signal Descriptions Below are the signal descriptions for the CN1/CN2 connectors: Signal Name Reference Direction Description AIGND — — Analog input ground. All three ground references (AIGND, AOGND, and DGND) are connected onboard. AI<0..15> (16-CH) PCI-69222 Analog Input AIGND Input Channels 0~15. -
Page 28: Ssi Connector Pin Assignment
Signal Name Reference Direction Description EZ<0, 1> Encoder Input Encoder Z Phase Ground ORG<0, 1> Encoder Input Encoder Original Signal Ground Encoder +24V Encoder Input Encoder voltage input pin Ground GPTC_CLK<0, 3> DGND Input GPTC<0, 3> clock source GPTC_GATE<0, 3> DGND Input GPTC<0, 3>... -
Page 29: Ssi Connector Signal Description
SSI Connector Signal Description Signal Name Setting Direction Description SSI_ADCONV Master Output Sends out the ADCONV Slave Input Accepts the SSI_ADCONV to replace the internal ADCONV signal SSI_AD_TRIG Master Output Sends the internal AD_TRIG out Slave Input Accepts the SSI_AD_TRIG as the digital trigger signal SSI_DAWR Master... -
Page 30: Analog Input Signal Connection
Analog Input Signal Connection The PCI-69222 provides up to 16 single-ended or 8 differential analog input channels, while the PCI-69223 offers up to 32 single- ended or 16 differential analog input channels. You can fill the Channel Gain Queue to get the desired input signal type combina- tion. -
Page 31: Input Configurations
Input Configurations Single-ended Connections A single-ended connection is used when the analog input sig- nal is referenced to a ground that can be shared with other analog input signals. There are two types of single-ended con- nections: RSE and NRSE configuration. In RSE configuration, the PCI-69222/PCI-69223 card provides the grounding point for external analog input signals and is suitable for floating sig- nal sources. -
Page 32: Figure 2-3: Ground-Referenced Sources And Nrse Input Connections
Non-Referenced Single-Ended (NRSE) Mode To measure ground-referenced signal sources, which are con- nected to the same ground point, you can connect the signals in NRSE mode. Figure 2-3 illustrates the connection. The signal’s local ground reference is connected to the negative input of the instru- mentation amplifier (AISENSE pin on CN1 connector), and the com- mon-mode ground potential between signal ground and the onboard ground will be rejected by the instrumentation amplifier. -
Page 33: Figure 2-5: Floating Source And Differential Input
Figure 2-5 shows how to connect a floating signal source to the PCI- 69222/PCI-69223 card in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equiv- alent source impedance. - Page 34 Hardware Information...
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Page 35: Installation
Installation Before You Proceed The PCI-69222/PCI-69223 card has electro-static sensitive com- ponents that can be easily damaged by static electricity. The card must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat. -
Page 36: Configuring The Card
6. Replace the system/chassis cover. 7. Connect the power plug to a power source, then turn on the system. Configuring the Card As a plug and play component, the card requests an interrupt number through its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. -
Page 37: Operation Theory
Operation Theory The operation theory of each function in the PCI-69222/PCI-69223 card is described in this chapter. These functions include A/D conversion, D/A conversion, encoder, programmable function I/O, and more. The operation theory can help you understand how to configure and program the PCI-69222/PCI-69223 card. Block Diagram There are 32/16 single-ended channels of 16-bit A/D input and 2 single-ended channels of 16-bit D/A output available in the PCI-... -
Page 38: A/D Conversion
waveform generation. The general purpose function digital IO and encoders are controlled directly by the FPGA. Refer to Figure 4-1. Figure 4-1: PCI-69222/PCI-69223 Block Diagram A/D Conversion When using an A/D converter, you must know about the properties of the signal to be measured and decide which channel to use and how to connect the signals to the card. -
Page 39: Ai Data Format
PCI-69222/PCI-69223 AI Circuitry Figure 4-2: PCI-69222/PCI-69223 AI Circuitry AI Data Format The data format of the acquired 16-bit A/D data is 2’s complement coding. Table 4-1 shows the valid input ranges and the ideal transfer characteristics. Digital Description Bipolar Analog Input Range code Full-scale Range ±10V... -
Page 40: Software Conversion With Polling Data Transfer
Digital Description Bipolar Analog Input Range code FSR-1LSB 1.249961V 0.999969V 0.499984V 0.249992V 7FFF Midscale +1LSB 38.14uV 30.51uV 15.25uV 7.62uV 0001 Midscale 0000 Midscale -1LSB -38.14uV -30.51uV -15.25uV -7.62uV FFFF -FSR -1.25V -0.5V -0.25V 8000 Table 4-2: Bipolar Analog Input Range and Output Digital Code Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling) Considered the most convenient way to acquire a single A/D data,... -
Page 41: Continuous Acquisition (Scanning) Mode
This method is suitable for applications that need to process A/D data in real time. In this mode, the timing of the A/D conversion is fully controlled by the software. The A/D conversion rate is decided by the software timer and may not be totally precise. In Software Polling, the channel, gain, and input configuration (RSE, NRSE, or DIFF) may be specified for each single-point measurement. -
Page 42: Figure 4-4: Scan Timing
SI_counter (32-bit) Specify the Scan Interval = SI_counter / Timebase SI2_counter (24-bit) Specify the Data Sampling Interval = SI2_counter/Timebase PSC_counter (31-bit) Specify the Post Scan Counts after a trigger event NumChan_counter (8-bit) Specify the number of samples per scan The acquisition timing and the meaning of the four counters are illustrated in Figure 4-4. - Page 43 NOTES • The maximum A/D sampling rate is 250 kHz for PCI-69222 and 500 kHz for PCI-69223. The minimum setting for the SI2_counter when using the internal Timebase is 320 (PCI-69222) and 160 (PCI- 69223). • The SI_counter is 32-bit while the SI2_counter is 24-bit. The maxi- mum scan interval using the internal Timebase = 2 /80 Ms = 53.687s, and the maximum sampling interval between two chan-...
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Page 44: Trigger Modes
Then: Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2, 0, 2 Sampling Interval = 160/80M s = 2 us Scan Interval = 640/80M s = 8 us Equivalent sampling rate of ch0, ch1: 125 kHz ... -
Page 45: Figure 4-6: Post Trigger With Retrigger
Post-Trigger Acquisition (with retrigger) post-trigger acquisition with retrigger function applications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC_counter and are programmable. Use Retrig_no to specify the re-trigger numbers. In Figure 4-6, two scans of data are acquired after the first trigger signal, then the card waits for the retrigger signal (retrigger signals which occur before the scans are completed will be ignored). -
Page 46: Bus-Mastering Dma Data Transfer
The four remaining scans are not performed until the trigger signal is disasserted again. The process repeats until the specified amount of retrigger signals are detected. total acquired data length NumChan_counter *PSC_counter. Figure 4-7: Gated Trigger with Finite Scan Acquisition Bus-mastering DMA Data Transfer In programmable scan acquisition mode, the PCI-69222/PCI- 69223 supports bus-mastering DMA data transfer. - Page 47 The DMA transfer mode is a very complex to program. It is recommended that you use a high-level program library provided by the JYTEK driver to configure this card. By using a high-level programming library for high speed DMA data acquisition, you simply need to assign the sampling period and the number of conversion through their specified counters.
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Page 48: Figure 4-8: Scatter-Gather Dma For Data Transfer
Figure 4-8: Scatter-gather DMA for Data Transfer In non-chaining mode, the maximum DMA data transfer size is 2M double words (8 MB). However, by using chaining mode-scatter/ gather, there is no limitation for the DMA data transfer size. You may also link the descriptor nodes circularly to achieve a multi- buffered mode DMA. -
Page 49: D/A Conversion
D/A Conversion complex applications, PCI-69222/PCI-69223 offers software polling to update the output, and DMA data transfer to generate waveform. This means that the D/A update rate is not only controlled by software timing, but can also be set by a precision hardware timer that you specified. -
Page 50: Figure 4-9: Fifo Data In/Out Structure
PCI-69223 operates waveform generation mode, waveform patterns are stored in FIFO with 512 samples. Waveform patterns larger than 512 samples are also supported using bus-mastering DMA transfer via the PCI controller. Data format in FIFO is shown in Figure 4-9. Figure 4-9: FIFO Data In/Out Structure DMA transfers data according to channel order. -
Page 51: Table 4-4: Summary Of Counters For Waveform Generation
You can choose the update clock source by setting the AO source configuration. Refer to Figure 4-11. It is recommended that you use the internal hardware to get a more precise update rate. Internal Timer AO update clock GPI[7..0] Figure 4-11: Waveform Generation Clock Source Selection Waveform Generation with Internal Hardware Timer Six counters interact with the waveform to generate different DAWR timing to form various waveforms. -
Page 52: Figure 4-12: Typical D/A Timing Of Waveform Generation
DLY2_counter 32-bit Defines the delay time Delay Time = to separate consecutive (DLY2_counter / Clock waveform generation. Timebase) This is applicable only in Iterative Waveform Generation mode. Trig_counter 32-bit Defines the acceptable start trigger count when re-trigger function is enabled Table 4-4: Summary of Counters for Waveform Generation Timebase*= 80M NOTE... -
Page 53: Figure 4-13: Post-Trigger Generation
Trigger Modes Post-Trigger Generation Use post-trigger generation when you want to generate a waveform right after a trigger signal. The number of patterns to be updated after the trigger signal is specified by UC_counter* IC_counter and is illustrated in Figure 4-13. Figure 4-13: Post-Trigger Generation Delay-Trigger Generation Use delay-trigger when you want to delay the waveform... -
Page 54: Figure 4-14: Delay-Trigger Generation
Figure 4-14: Delay-Trigger Generation Post-Trigger or Delay-Trigger with Retrigger Use post-trigger or delay-trigger with retrigger when you want to generate multiple waveforms with respect to multiple incoming trigger signals. You can set Trig_counter to specify the number of acceptable trigger signals. Refer to Figure 4-15. In this example, two waveforms are generated after the first trigger signal. -
Page 55: Figure 4-15: Post-Trigger With Retrigger Generation
Figure 4-15: Post-Trigger with Retrigger Generation NOTE Start Trigger signals asserted during the waveform gen- eration process will be ignored. Iterative Waveform Generation You can set the IC_counter to generate iterative waveforms regardless of the trigger mode used. The IC_counter stores the iteration number. -
Page 56: Figure 4-16: Finite Iterative Waveform Generation With Post-Trigger
computer’s memory via DMA, and will occupy the PCI bandwidth. If the value specified in UC_counter is smaller than the sample size of the waveform patterns, the waveform will be generated piece-wisely. For example, if you defined a 16-sample sine wave and set the UC_counter to 2, the generated waveform will be a 1/8-cycle sine wave for every waveform period, and a complete sine wave will be generated for every 8-iterations. -
Page 57: Figure 4-17: Infinite Iterative Waveform Generation With Post-Trigger
Figure 4-17: Infinite Iterative Waveform Generation with Post-trigger In conjunction with different trigger modes and counter setups, you can manipulate a single waveform to generate different and more complex waveforms. DLY2_Counter in Iterative Waveform Generation To expand the flexibility of iterative waveform generation, DLY2_counter implemented separate... -
Page 58: Programmable Function I/O
Programmable Function I/O PCI-69222/PCI-69223 supports powerful programmable function I/O provided by an FPGA chip. These function I/O can be configured as TTL DI/DO or 32-bit timer/counters. In addition, the timer/counter supports a variety of modes, including general purpose timer/counter, PWM output, or encoder input for simple motion control. -
Page 59: General Purpose Timer/Counter
General Purpose Timer/Counter The PCI-69222/PCI-69223 comes with three general purpose timer/counter sets featuring: Count up/down controlled by hardware or software Programmable counter clock source (internal clock up to 80 MHz, external clock up to 10 MHz) Programmable gate selection (hardware or software control) ... -
Page 60: General Purpose Timer/Counter Modes
controls the counter to count up or down (high: count up; low: count down), while the GPTC_GATE input is a control signal which acts as a counter enable or a counter trigger signal under different applications. The GPTC_OUT will then generate a pulse signal based on which timer/counter mode you have set. -
Page 61: Figure 4-19: Mode 2 Operation
Mode 2: Single Period Measurement The counter counts the period of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from the software application. After the software-start, the counter counts the number of active edges on GPTC_CLK between two active edges of GPTC_GATE. -
Page 62: Figure 4-20: Mode 3 Operation
Figure 4-20: Mode 3 Operation Mode 4: Single Gated Pulse Generation This generates a single pulse with programmable delay and programmable pulse-width following the software-start. The two programmable parameters can be specified in terms of periods of the GPTC_CLK input by the software application. GPTC_GATE enable/disable counting. -
Page 63: Figure 4-22: Mode 5 Operation
Mode 5: Single Triggered Pulse Generation This mode generates a single pulse with programmable delay programmable pulse-width following active GPTC_GATE edge. specify these programmable parameters in terms of periods of the GPTC_CLK input. When first GPTC_GATE edge triggers single pulse, GPTC_GATE makes effect... -
Page 64: Figure 4-24: Mode 7 Operation
Mode 7: Single Triggered Continuous Pulse Generation This mode is similar to Mode 5 except that the counter generates continuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC_GATE. When the first GPTC_GATE edge triggers the counter, GPTC_GATE makes no effect until the software-start is executed again. -
Page 65: Figure 4-26: Mode 9 Operation
Mode 9: Edge Separation Measurement Measures the time differentiation between two different pulse signals. The first pulse signal is connected to GPTC_GATE and the second signal is connected to GPTC_AUX. It counts the clocks that pass by between the rising edge signal of two different pulses through the 40MHz internal clock or external clock. -
Page 66: Digital Waveform Acquisition And Generation
Digital Waveform Acquisition and Generation The PCI-69222/PCI-69223 GPI and GPO support digital waveform generation and digital waveform acquisition. You can sample GPI or update GPO based on the precision hardware timer. Digital Waveform Acquisition The digital data on GPI channels can be acquired by using the digital waveform acquisition mode. -
Page 67: Figure 4-28: Digital Waveform Acquisition Operation
Figure 4-28: Digital Waveform Acquisition Operation Digital Waveform Generation The digital output on GPO [15..0] channels can be updated by using digital waveform generation mode. This works similar to AO waveform generation. With periodic update clock, you can generate a sequence of digital output patterns based on precision hardware time interval. -
Page 68: Isolation Encoder
Isolation Encoder PCI-69222/PCI-69223 features combination data acquisition and simple motion control with support for two channel encoder input sets which provide an alternative for step motor or servo motor's position feedback. The encoder sets are assigned in CN2. Definition Pin # Definition E24V EGND... -
Page 69: Figure 4-31: Encoder Ogrx Input
The Encoder OGRx input is different from the encoder phase input since you need to add an external +24V power to drive the photo-couple. Figure 4-31 shows the OGRx input. Figure 4-31: Encoder OGRx Input CW/CCW Encoder Mode When GPTC is set to CW/CCW encoder mode and when the input EAx is connected to CW source signal and EBx is connected to CCW source signal, pulses from EAx will cause the counter to counter up and spin the motor clockwise. -
Page 70: Figure 4-33: X1 Encoder Mode
X1 Encoder Mode In X1 encoder mode, if phase A (EA0/EA1) is advanced of phase B (EB0/EB1) in a quadrature cycle, the increment of counter value will be 1. Otherwise, if phase B is advanced of phase A in a quadrature cycle, the decrement of counter value will also be 1. -
Page 71: Figure 4-35: X4 Encoder Mode
X4 Encoder Mode This mode is similar to X1 Encoder Mode, except that the amount of counter value increases or decreases by four. Refer to Figure 4-35. Figure 4-35: X4 Encoder Mode Phase Z Each encoder mode may use a third phase, phase Z, that is also frequently used for the index phase. -
Page 72: Figure 4-36: Phase Z
Figure 4-36: Phase Z Original Signal (ORGx) Original Signal (ORG0/ORG2/ORG1) is used with phase Z. With ORG enabled, a high level on phase Z and ORG causes the counter to reload with a specified value in a specified phase of the quadrature cycle. When you use ORG signal if it is at a low level and phase Z is at a high level, then counter reload is ignored. -
Page 73: Trigger Sources
PCI-69223 function I/O. You can set any DI line as external trigger pin. You may also easily program the trigger polarity via the JYTEK software drivers. Take note that the signal level of the external digital trigger signals should be TTL-compatible with a minimum 25 ns pulse. - Page 74 Operation Theory...
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Page 75: Calibration
Calibration This chapter introduces the card calibration process to minimize AD measurement errors and DA output errors. Loading Calibration Constants The PCI-69222/PCI-69223 is factory-calibrated before shipment. The associated calibration constants of the TrimDACs firmware are written to the onboard EEPROM. TrimDACs firmware is the algorithm in the FPGA. -
Page 76: Saving Calibration Constants
Saving Calibration Constants Factory-calibrated constants are permanently stored in a bank of the onboard EEPROM and may not be modified. When you re-cal- ibrate the device, the software stores the new constants in a user- configurable section of the EEPROM. To return a device to its ini- tial factory calibration settings, the software can copy the factory calibrated constants to the user-configurable section of the EEPROM. -
Page 77: Warranty Policy
For products containing storage devices (hard drives, flash cards, etc.), please back up your data before send- ing them for repair. JYTEK is not responsible for any loss of data. Please ensure the use of properly licensed software with ... - Page 78 2. Our repair service is not covered by JYTEK's guarantee in the following situations: Damage caused by not following instructions in the User's Manual. Damage caused by carelessness on the user's part during product transportation. Damage caused by fire, earthquakes, floods, lightening, ...
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Page 79: Getting Service
Getting Service Customer satisfaction is our top priority. Contact us should you require any service or assistance. SHANGHAI JYTEK CO.,LTD. Web Site http://www.jytek.com Sales & Service service@jytek.com Telephone No. +86-21-50475899 Fax No. +86-21-50475899 Mailing Address 300 Fang chun Rd., Zhangjiang Hi-Tech... - Page 80 Getting Service...
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