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U4
U5
U6
U7
U10
U11
U12
U13
U14
U16
U17
U18
U19
U20
U21
U29
U30
U31
U32
U46
U50
U51
U52
U53
XBT
XMM1
XMM2 - XMM5
XU1
XU2
XU15/U15
XU19/U19
Y1
Y2
Y3
96
Appendix D System Board and Riser Board Reference Designators
South bridge
Super I/O
Clock chip
64 bit Bridge
LOM1
LOM1 EEPROM
LOM1 PHY
Audio Codec
Audio amplifier
LOM2
LOM2 EEPROM
LOM2 PHY
SPI ROM - SOIC-8 footprint
Fan controller
SPI ROM - SO16 footprint
TMDS controller
Parallel port diode array
First serial port transceiver
Second serial port transceiver
VRM controller
USB front port power switch
First USB rear port power switch
Second USB rear port power switch
Third USB rear port power switch
Battery retainer
Memory slot. DIMM1 or RIMM1 populated and tested
Following memory slots
Primary processor socket
Secondary processor socket
System ROM and Socket (Socket = XU15, ROM = U15)
SPI ROM and socket (XU19 = socket, U19 = SPI ROM)
Primary (TH) system clock crystal
Secondary (SMT) system clock crystal
Primary NIC clock crystal
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