Texas Instruments TRF7964A Manual

Multiprotocol fully integrated 13.56-mhz rfid reader and writer ic

Hide thumbs

Table Of Contents

Table of Contents

Quick Links

Download this manual

TRF7964A Multiprotocol Fully Integrated 13.56-MHz RFID Reader and Writer IC

1 Device Overview

1.1

Features

• Completely Integrated Protocol Handling for

ISO15693, ISO18000-3, ISO14443A/B, and

FeliCa™

• Integrated State Machine for ISO14443A

Anticollision (Broken Bytes) Operation

• Input Voltage Range: 2.7 VDC to 5.5 VDC

• Programmable Output Power: +20 dBm (100 mW),

+23 dBm (200 mW)

• Programmable I/O Voltage Levels From 1.8 VDC

to 5.5 VDC

• Programmable System Clock Frequency Output

(RF, RF/2, RF/4) from 13.56-MHz or 27.12-MHz

Crystal or Oscillator

1.2

Applications

•

Public Transport or Event Ticketing

•

Passport or Payment (POS) Reader Systems

•

Product Identification or Authentication

1.3

Description

The TRF7964A device is an integrated analog front end and data-framing device for a 13.56-MHz RFID

system. Built-in programming options make the device suitable for a wide range of applications for

proximity and vicinity identification systems.

Built-in user-configurable programming options make the device suitable for a wide range of applications.

The TRF7964A device is configured by selecting the desired protocol in the control registers. Direct

access to all control registers allows fine tuning of various reader parameters as needed.

Documentation, reference designs, EVM, and source code TI MSP430™ MCUs or ARM

available.

PART NUMBER

TRF7964ARHB

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Sample &

Product

Buy

Folder

Device Information

Tools &

Technical

Software

Documents

• Integrated Voltage Regulator Output for Other

System Components (MCU, Peripherals,

Indicators), 20 mA (Max)

• Programmable Modulation Depth

• Dual Receiver Architecture With RSSI for

Elimination of "Read Holes" and Adjacent Reader

System or Ambient In-Band Noise Detection

• Programmable Power Modes for Ultra Low-Power

System Design (Power Down <1 µA)

• Parallel or SPI Interface (With 127-Byte FIFO)

• Temperature Range: –40°C to 110°C

• 32-Pin QFN Package (5 mm x 5 mm)

•

Medical Equipment or Consumables

•

Access Control, Digital Door Locks

PACKAGE

VQFN (32)

Support &

Community

TRF7964A

SLOS787H – MAY 2012 – REVISED APRIL 2014

MCUs are

BODY SIZE

5 mm x 5 mm

Table of Contents

Need help?

Do you have a question about the TRF7964A and is the answer not in the manual?

Questions and answers

Summary of Contents for Texas Instruments TRF7964A

Page 1: Device Overview
Product Identification or Authentication Description The TRF7964A device is an integrated analog front end and data-framing device for a 13.56-MHz RFID system. Built-in programming options make the device suitable for a wide range of applications for proximity and vicinity identification systems.
Page 2: Functional Block Diagram
STATE MACHINE ASK/OOK VSS_RF VOLTAGE SUPPLY REGULATOR SYSTEMS (SUPPLY REGULATORS AND REFERENCE VOLTAGES) VDD_X OSC_IN CRYSTAL OR OSCILLATOR TIMING SYSTEM VSS_D OSC_OUT Figure 1-1. Block Diagram Device Overview Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 3: Table Of Contents
Terminal Functions .......... Considerations ..........Specifications TRF7964A Reader System Using Parallel ............Absolute Maximum Ratings Microcontroller Interface ....TRF7964A Reader System Using SPI With SS Recommended Operating Conditions ..........Mode ......Electrical Characteristics ......Layout Considerations ........Handling Ratings ..
Page 4: Revision History
Deleted previous Section 10, System Design, and moved contents to Section 7.3 through Section 7.5 ................• Removed references to figure numbers in Figure 7-3 Revision History Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 5: Device Characteristics
TRF7964A www.ti.com SLOS787H – MAY 2012 – REVISED APRIL 2014 3 Device Characteristics Table 3-1 shows the supported modes of operation for the TRF7964A device. Table 3-1. Supported Protocols Supported Protocols ISO-14443A/B FeliCa ISO-15693, Device ISO-18000-3 212 kbps, 106 kbps...
Page 6: Terminal Configuration And Functions
32-pin RHB package. VDD_A I/0_7 I/0_6 VDD_RF I/0_5 VDD_PA I/0_4 TX_OUT I/0_3 VSS_PA I/0_2 VSS_RX I/0_1 RX_IN1 I/0_0 Figure 4-1. 32-Pin RHB Package (Top View) Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 7: Terminal Functions
Chip enable input (If EN = 0, then chip is in sleep or power-down mode). Negative supply for internal digital circuits SS_D (1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 8 Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, DD_X MCU) Thermal Pad Chip substrate ground Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 9: Specifications
Input voltage - logic low EN, EN2, ASK/OOK, MOD DD_I/O I/O lines, IRQ, SYS_CLK, DATA_CLK, 0.8 x Input voltage threshold, logic high EN, EN2, ASK/OOK, MOD DD_I/O Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 10: Electrical Characteristics
10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load used). Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
Page 11: Handling Ratings
10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load used). Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
Page 12: Detailed Description
127-byte FIFO register. For direct transmit or receive functions, the encoders and decoders can be bypassed so that the MCU can process the data in real time. The TRF7964A supports data communication voltage levels from 1.8 V to 5.5 V for the MCU I/O interface. The transmitter has selectable output-power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω...
Page 13: System Block Diagram
SLOS787H – MAY 2012 – REVISED APRIL 2014 The transmitter supports OOK and ASK modulation with selectable modulation depth. The TRF7964A also includes a data transmission engine that comprises low-level encoding for ISO15693, ISO14443A/B and FeliCa. Included with the transmit data coding is the automatic generation of Start Of Frame (SOF), End Of Frame (EOF), Cyclic Redundancy Check (CRC), or parity bits.
Page 14 DD_A DD_X bypass capacitors for supply noise filtering must be used (per reference schematics). NOTE must be the highest voltage supplied to the TRF7964A. RF Power Amplifier Regulator: V DD_RF The V (pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for DD_RF either 5-V or 3-V operation.
Page 15 SLOS787H – MAY 2012 – REVISED APRIL 2014 Power Amplifier Supply: V DD_PA The power amplifier of the TRF7964A is supplied through V (pin 4). The positive supply pin for the RF DD_PA power amplifier is externally connected to the regulator output V (pin 3).
Page 16 . This ensures the highest possible supply DD_RF DD_A DD_X voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio). Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 17 (thus unable to control the EN input). A rising edge applied to the EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56- MHz oscillator (identical to condition EN = 1). Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 18 Modes 3 and 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the normal modes used for normal transmit and receive operations. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
Page 19: Receiver - Analog Section
6.4.1 Main and Auxiliary Receivers The TRF7964A has two receiver inputs: RX_IN1 (pin 8) and RX_IN2 (pin 9). Each of the input is connected to an external capacitive voltage divider to ensure that the modulated signal from the tag is available on at least one of the two inputs.
Page 20: Receiver - Digital Section
ISO14443B 106 kbps, ISO14443A/B data-rates of 212 kbps and 424 kbps and FeliCa 424 kbps. Receiver – Digital Section The output of the TRF7964A analog receiver block is a digitized subcarrier signal and is the input to the digital receiver block. This block includes a Protocol Bit Decoder section and the Framing Logic section.
Page 21 The nature of the interrupt request pulse is available in the IRQ and Status register (address 0x0C). The bit coding description of this register is shown in Section 6.13.3.3.1. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 22 RX rate (see register 0x03) ISO14443 B high bit rate 424 kbps ISO14443 B high bit rate 848 kbps Reserved Reserved FeliCa 212 kbps FeliCa 424 kbps Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 23 SLOS787H – MAY 2012 – REVISED APRIL 2014 6.5.1 Received Signal Strength Indicator (RSSI) The TRF7964A incorporates in total three independent RSSI building blocks: Internal Main RSSI, Internal Auxiliary RSSI, and External RSSI. The internal RSSI blocks are measuring the amplitude of the subcarrier signal;...
Page 24: Oscillator Section
The external shunt capacitors are calculated as two identical capacitors in series plus the stray capacitance of the TRF7964A and parasitic PCB capacitance in parallel to the crystal. The parasitic capacitance (C , stray and parasitic PCB capacitance) can be estimated at 4 to 5 pF (typical).
Page 25: Transmitter - Analog Section
External control of the transmit modulation depth is possible by setting the ISO Control register (0x01) to direct mode. While operating the TRF7964A in direct mode, the transmit modulation is made possible by selecting the modulation type ASK or OOK at pin 12. External control of the modulation type is made possible only if enabled by setting B6 in the Modulator and SYS_CLK Control register (0x09) to 1.
Page 26: Transmitter - Digital Section
The digital part of the transmitter is a mirror of the receiver. The settings controlled the ISO Control register (0x01) are applied to the transmitter just like the receiver. In the TRF7964A default mode the TRF7964A automatically adds these special signals: start of communication, end of communication, SOF, EOF, parity bits, and CRC bytes.
Page 27 = 0 enables a digital output, B3 = 1 enables an analog output). The design of an external power amplifier requires detailed RF knowledge. There are also readily designed and certified high-power HF reader modules on the market. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 28: Trf7964A Ic Communication Interface
When the SPI interface is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hard-wired as shown Table 6-9. At power up, the TRF7964A samples the status of these three pins and then enters one of the possible SPI modes.
Page 29 The Command Mode is used to enter a command resulting in reader action (for example, initialize transmission, enable reader, and turn reader on or off). Examples of expected communications between an MCU and the TRF7964A are shown in the following sections.
Page 30 Figure 6-8. Continuous Address Register Write Example Starting with Register 0x00 Using SPI With SS Figure 6-9. Continuous Address Register Read Example Starting with Register 0x00 Using SPI With SS Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
Page 31 Figure 6-10. Single Address Register Write Example of Register 0x00 Using SPI With SS Figure 6-11. Single Address Register Read Example of Register 0x00 Using SPI With SS Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
Page 32 Cmd x (Optional data or command) Stop Figure 6-12. Direct Command Example of Sending 0x0F (Reset) Using SPI With SS The other Direct Command Codes from MCU to TRF7964A IC are described in Section 6.12. 6.10.1.4 FIFO Operation The FIFO is a 127-byte register at address 0x1F with byte storage locations 0 to 126. FIFO data is loaded...
Page 33 SLOS787H – MAY 2012 – REVISED APRIL 2014 During transmission, the MCU loads the TRF7964A IC's FIFO (or during reception the MCU removes data from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile, the byte counter keeps track of the number of bytes being transmitted.
Page 34 If the reader detects a receive error, the corresponding error flag is set (framing error, CRC error) in the IRQ Status register, indicating to the MCU that reception was not completed correctly. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
Page 35 When an SPI interface is used, I/O pins I/O_2, I/O_1, and I/O_0 must be hard wired according to Table 6- 9. On power up, the TRF7964A looks for the status of these pins and then enters into the corresponding mode.
Page 36 No Data Transitions (All High or Low) Ignore Don’t Care MISO SLAVE SELECT Figure 6-17. Procedure for Dummy Read Figure 6-18. Example of Dummy Read Using SPI With SS Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 37 No Data Transitions (All High or Low) No Data Transitions (All High or Low) MISO DON’T CARE SLAVE SELECT Figure 6-20. Continuous Read Operation Using SPI With Slave Select Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 38 Figure 6-22. Inventory Command Sent From MCU to TRF7964A The TRF7964A takes these bytes from the MCU and then send out Request Flags, Inventory Command ,and Mask over the air to the ISO15693 transponder. After these three bytes have been transmitted, an interrupt occurs to indicate back to the reader that the transmission has been completed.
Page 39 The next byte is the DSFID (usually shipped by manufacturer as 0x00), then the UID, shown here up to the next most significant byte, the MFG code (shown as 0x07 (TI silicon)). Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
Page 40 At this point, it is good form to reset the FIFO and then read out the RSSI value of the tag. In this case the transponder is very close to the antenna, so value of 0x7F is recovered. Figure 6-26. Reset FIFO and Read RSSI Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 41 ISO standard communications, then deviated from the standard after being identified and selected, the ability to go into Direct Mode 0 becomes very useful. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
Page 42 Step 1: Configure Pins I/O_0 to I/O_2 for SPI with SS Step 2: Set Pin 12 of the TRF7964A (ASK/OOK pin) to 0 for ASK or 1 for OOK Step 3: Program the TRF7964A registers The following registers need to be explicitly set before going into the Direct Mode.
Page 43 3. Set bit B6 of the Chip Status Control register (0x00) to 1 to enter Direct Mode 4. Send extra eight clock cycles (see Figure 6-28, this step is TRF7964A specific) NOTE – It is important that the last write is not terminated with a stop condition. For SPI, this means that Slave Select (I/O_4) stays low.
Page 44 The receive data bytes must be buffered locally. As an example of the receive data bits and framing level according to the ISO14443A standard is shown Figure 6-31 (taken from ISO14443 specification and TRF7964A air interface). Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated...
Page 46: Special Direct Mode For Improved Mifare™ Compatibility
Step 7: Terminating Direct Mode 0 After the EOF is received, data transmission is over, and Direct Mode 0 can be terminated by sending a Stop Condition (in the case of SPI, make the Slave Select go high). The TRF7964A is returned to default state.
Page 47 0x00 0x0D Collision position and interrupt mask 0x3E 0x0E Collision position 0x00 0x0F RSSI levels and oscillator status 0x40 (1) Differs from default at POR Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 48 TX if the RX wait time register (0x08) is set. In this case, the receiver is enabled at the end of the wait time following the transmit operation. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
Page 49 Tag communication for the Check RF command to work properly. Table 6-18. Test External RF Peak Level to RSSI Codes RF_IN1 [mV Decimal Code Binary Code Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 50: Register Description
Special Function Register, Preset 0x00 0x14 Adjustable FIFO IRQ Levels Register Status Registers 0x0C IRQ status 0x0D Collision position and interrupt mask register 0x0E Collision position Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 51 Test Register. Preset 0x00 0x1B Test Register. Preset 0x00 FIFO Registers 0x1C FIFO status 0x1D TX length byte 1 0x1E TX length byte 2 0x1F FIFO I/O register Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 52 RFID application RFID: See Table 6-22 for B0:B4 settings based on ISO protocol desired by iso_2 RFID application (1) Only applicable to ISO-14443A and ISO-15693 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 53 FeliCa 212 kbps FeliCa 424 kbps (1) For ISO14443A/B, when bit rate of TX is different from RX, settings can be done in register 0x02 or 0x03. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 54 TX For 14443A high bit rate, coding and decoding 1 = parity odd except last parity-2rx byte which is even for RX Unused Unused Unused Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 55 Timer Length All bits low = timer disabled (0x00) tm_length2 Timer Length tm_length1 Timer Length Preset 0x00 for all other protocols tm_length0 Timer Length LSB Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 56 604 µs → Reserved 755 µs → ISO15693 high data rate (TI Tag-It HF-I) NoResp0 No response LSB 1812 µs → ISO15693 low data rate (TI Tag-It HF-I) Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 57 Rxw3 9.44 µs → FeliCa Rxw2 66 µs → ISO14443A and B Rxw1 180 µs → Reserved Rxw0 293 µs → ISO15693 (TI Tag-It HF-I) Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 58 The frequency of SYS_CLK (pin 27) is programmable by the bits B4 and B5 of this register. The frequency of the TRF7964A system clock oscillator is divided by 1, 2 or 4 resulting in available SYS_CLK frequencies of 13.56 MHz or 6.78 MHz or 3.39 MHz.
Page 59 The setting of bits B4, B5, B6 and B7 to zero selects bandpass characteristic of 240 kHz to 1.4 MHz. This is appropriate for ISO14443B, FeliCa protocol, and ISO14443A higher bit rates 212 kbps and 424 kbps. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 60 DD_X = 2.8 V, V and V = 2.8 V DD_RF DD_A DD_X = 2.7 V, V and V = 2.7 V DD_RF DD_A DD_X Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 61 Table 6-37. IRQ Status Register (0x0C) Function: Information available about TRF7964A IRQ and TX/RX status Default: 0x00 at POR = H or EN = L, and at each write to the ISO Control Register 0x01. It is also automatically reset at the end of a read phase.
Page 62 ISO14443A mainly supported, in the other protocols this register shows the bit position of error. Either frame, SOF/EOF, parity or CRC error. Col3 Col2 Col1 Col0 Bit position of collision LSB Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 63 0 = 7 subcarrier pulses Selects the number of subcarrier pulses that trigger collision error in the col_7_6 1 = 6 subcarrier pulses 14443A - 106 kbps Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 64 Reserved Reserved Reserved Wlh_1 Wlh_1 Wlh_0 IRQ Level FIFO high IRQ level (during Wlh_0 Wll_1 Wll_1 Wll_0 IRQ Level FIFO low IRQ level (during Wll_0 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 65 Description test_rf_level RF level test test_io1 I/O test Not implemented test_io0 test_dec Decoder test mode clock_su Coder clock 13.56 MHz For faster test of coders Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 66 Bits B0:B6 indicate how many bytes that are in the FIFO to be read out (= N number of bytes, in hex) FIFO bytes fb[1] FIFO bytes fb[0] Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 67 It is taken into account only when broken byte flag is set. Broken byte number of bits bb[0] Broken byte flag B0 = 1, indicates that last byte is not complete 8 bits wide. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 68: Application Schematic And Layout Considerations
TRF7964A application schematic. Both ISO15693, ISO14443 and FeliCa systems can be addressed. Due to the low clock frequency on the DATA_CLK line, the parallel interface is the most robust way to connect the TRF7964A with the MCU. Figure 7-1 shows matching to a 50-Ω...
Page 69: Trf7964A Reader System Using Spi With Ss Mode
7.2.1 General Application Considerations Figure 7-2 shows the TRF7964A application schematic optimized for both ISO15693 and ISO14443 systems using the Serial Port Interface (SPI). Short SPI lines, proper isolation of radio frequency lines, and a proper ground area are essential to avoid interference. The recommended clock frequency on the DATA_CLK line is 2 MHz.
Page 70: Layout Considerations
Impedance Matching TX_Out (Pin 5) to 50 Ω The output impedance of the TRF7964A when operated at full power out setting is nominally 4 + j0 (4 Ω real). This impedance must be matched to a resonant circuit and TI recommends matching circuit from 4 Ω...
Page 71 SLOS787H – MAY 2012 – REVISED APRIL 2014 Figure 7-3. Impedance Matching Circuit This yields the Smith Chart Simulation shown in Figure 7-4. Figure 7-4. Smith Chart Simulation Application Schematic and Layout Considerations Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7964A...
Page 72: Reader Antenna Design Guidelines
Table 6-20. Reader Antenna Design Guidelines For HF antenna design considerations using the TRF7964A, see these documents: • Antenna Matching for the TRF7960 RFID Reader (SLOA135) • TRF7960TB HF RFID Reader Module User's Guide (SLOU297) Application Schematic and Layout Considerations Copyright ©...
Page 73: Device And Documentation Support
All other trademarks are the property of their respective owners. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
Page 74 PACKAGE OPTION ADDENDUM www.ti.com 24-Oct-2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) TRF7964ARHBR ACTIVE VQFN 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 110 &...
Page 75 PACKAGE OPTION ADDENDUM www.ti.com 24-Oct-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2...
Page 79 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

This manual is also suitable for:

Trf7964arhb

Texas Instruments TRF7964A Manual

Quick Links

1 Device Overview

Features

Applications

Description

Need help?

Questions and answers

Related Manuals for Texas Instruments TRF7964A

Summary of Contents for Texas Instruments TRF7964A

This manual is also suitable for:

Table of Contents