HP OmniBook 4000 Familiarization Manual page 45

Beep Code
none
1-1-1
1-1-3
1-1-4
1-2-1
1-2-2
1-2-3
1-3-1
1-3-2
none
1-3-3
1-4-2
2-1-1/2/3/4
2-2-1/2/3/4
2-3-1/2/3/4
2-4-1/2/3/4
3-1-1
Description
CPU register test in progress or failure.
CPU Failure
CMOS write/read test in progress or failure. Failure will result
in a system halt.
ROM BIOS checksum test in progress or failure. Failure will
result in a system halt. Checksum test - All of the values in a
given range of locations are added together. The range
includes a location which, when added to sum of the ranges,
will produce a known result (0). BIOS is in FLASH and can
only be fixed through replacement of the flash device (not a
field repairable item) Customer units should be returned for
repair.
Programmable interval timer 0 test in progress or failure.
Failure will result in a system
DMA channel 0 address and count register test in progress or
failure. Failure will result in a system halt.
DMA page register write/read test in progress or failure.
Failure will result in a system halt.
RAM refresh verification test in progress or failure. Failure will
result in a system halt.
SMI RAM Bad. Failure will result in a system halt.
First 64K RAM test in progress. No specific test is performed
- just indicates that the test is beginning (i.e., no failure).
First 64K RAM chip or data line failure, multi-bit. Failure
results in a system halt.
Parity failure first 64K RAM. Failure results in a system halt.
First 64K RAM chip or data line failure on bit x. Failure results
in a system halt.
Slave DMA register test in progress or failure. Failure results
in a system halt.
___________
45