Clocks - Compaq Armada e500 Series Reference Manual

Super I/O Controller
The Super I/O Controller device is the SMC FDC37N97 (MSIO). It integrates a new
generation of complete Super I/O functions, plus an enhanced 8051 microcontroller for
power management and keyboard control. The MSIO resides on the SUB-ISA bus and
includes the following features:
3.3-volt operation with 5-volt tolerant buffers


ACPI 1.0 and PC99-compliant


Three power planes


ACPI embedded controller interface


Low standby current in sleep mode


Configuration Register Set compatible with ISA Plug-and-Play


standard (version 1.0a)
Serial IRQ interface compatible with serialized IRQ support for PCI systems


Diskette interface on parallel port


8051 controller using parallel port to reprogram the flash ROM


Advanced infrared communications controller (IrCC 2.0)


512-kbyte flash ROM interface


ISA Host interface with clock run support and ACPI SCI interface


High-performance embedded 8051 keyboard and system controller


Four independent hardware-driven PS/2 ports


Intelligent Auto Power Management


1.44-MB Super I/O diskette controller


IEEE 1284-compliant parallel port with EPP and ECP support


Shared ROM interface so that the external 8051 Flash ROM can be shared with


system BIOS and SM firmware
For more detailed information about the MSIO, refer to Chapter 5.

Clocks

Clock Synthesizer and Clock Buffer
The clock synthesizer and SDRAM clock buffer are CK100-SM compliant
components.
The clock generator provides the clocks and low-skew distribution buffers required to
drive the Pentium II Processor, 440BX, SDRAM memory, PCI buses, ISA bus and
USB. A 14.381 MHz clock crystal provides the reference clock for an internal PLL that
generates all other frequencies. The device is operated at a +3.3-volt core voltage with
the outputs being at +2.5 volts and +3.3 volts.
2-16 Processor, Cache, and System Support