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9. Block Diagram
9-1 M51A (SP403JHP)
# MAIN TUNER : [ TECC2949PG30A(S) ]
+9V
+5V
+33V
AGC
SW AS
SCL
N.C
N.C
IF
SDA
2
I
C
SAW-VIF
SAW-SIF
# PIP TUNER : [ TECC2849PG29A(S) ]
+5V
+33V
MULTI
AGC
N.C
AS
SCL SDA
N.C
N.C
IF
2
I
C
CVBS
S C A R T 1
+5V
+8V
+12V
RCA2
-> AV ->TERMINAL ->MICOM BOARD
PIP MODULE
RCA3
CVBS-TTX
CVBS(A/V)
6
Y
SIDE
A/V
SDA
R-Y
4
TDA9160A
SDA9187-
SCART
1,2,3
SCL
B-Y
2X
S C A R T 1
UV
Y
IF
CVBS2
PAP102
SDA
TDA9815
SAW-VIF
SDA9189X
RGB F/B
SCL
K6263K
HS2P
VS2P
RGB F/B
RMC
KEYs Matrix
+5V
Proscan MICOM
MODULE
QPSK-INPUT
CVBS
2HS/VS
DRAM
SDA5273P
KM44C1004
MEGA
TEXT
OSD/TTX
RGB-OUTPUT
SCL2/SDA2
ZIEMENS
EEPROM
24W16
MICOM
SDA30C264
EPROM
64SDIP
27CD40
OSD-R
OSD-G
I
2
C-BUS
S-DATA
OSD-B
S-CLOCK
OSD-FB
SCL1/SDA1
S-ENABLE
I
2
C-BUS
SCART1
SCL2/SDA2
AM-INPUT
SCL2/SDA2
RCA3
SAA1300
DET-Err
SCART1
.TEMP
.FAN
PCF8574
RCA2
.LEVER
.LAMP
RCA3
F-A/V
RCA2
Samsung Electronics
F E AT UR E B OX
+5V
IIC
R.F PHONE JACK CABLE
27MHZ
15KHz
V PC 3 2 1 5
HS1
K6263K
50Hz
VS1
2CH ADC
K9462M
CVBS/Y
COLOR DECODER
CHROMA
COMBFILTER
STANDARD
IF
VIDEO-OUT
CLOCK SYNC GENERATOR
T D A 9 8 1 0
CVBS/Y
T D A 6 9 2 0
CHROMA
VIDEO
SOURCE
31KHZ
2HS
SELECT
RGB F/B
R/G/B
VS
IDENTIFY
PCF8591
Progressive
8BIT A/D & D/A CONNVERTER
T E A5 1 1 4
S DA9 2 8 0
R/G/B
SW
DISPLAY P ROCESSOR
Y
TRIPLE DAC
B-Y
T E A5 1 1 4
P E AKI NG/CTI
R-Y
R/G/B
SW
+5V
IIC
SOUND
+5V
+8V
MSP3410D
SOUND
PROCESSOR
DPL3519
IIS
DOLBY PRO
LOGIC
+5V IIC
H-SYNC V-SYNC
FORMATC4:2:2
50Hz
C I P 3 2 5 0 P
DIGITAL
Y.U.V
COMPONENT INTERFACE
P ROCESSOR
FORMAT4:1:1
50HZ
DIGITAL
Y.U.V
T DA4 7 8 0
RGB Video
Y.U.V
S DA9 2 7 2
S DA9 2 5 3
TRIPLE
VIP
FIELD
Y,B-Y,R-Y
MEMORY
MOTIONDE TECTOR
+5V
NOISE RE DUCTI ON
FLICKER -
Y.U.V
S DA9 2 5 3
RE DUCTI ON
TRIPLE
FIELD
MEMORY
+5V
FORMAT4:1:1
50HZ
+5V
IIC
DIGITAL
Y.U.V
MODULE
TDA7050
MAIN L.R
TL620DT
CENTER
CENTER
TC4053BP
SOUND S/W
TL620DT
SURROUND L.R
+5V
TC4052BC
+8V
SOUND S/W
L CD C ONT R O L B OAR D
2
C
+12V
I
+15.5V
WID SIG.
+15.5V
+13.5V
H: 16:9
+13.5V
+5V[A]
TDA8444
+5V[D]
L: 4:3
+5V
+5V[A]
3EA
R1/G1/B1
R2/G2/B2
R/G/B
R/G/B
S/H DRIVER
L CD P ANE L
C XA1 8 5 3 Q
C XA2 5 0 4 N
1 60 0 H X 4 80 V
LCD DRIVER
Procssor
L CX 0 1 1 A M
TIMMING
GEN. IC
2Hsync
74HC04
C XD2 4 4 3 Q
1Vsync
ASPECT RATIO :16:9
INVERT
S-DATA
+5V[D]
+5V
SAND-CASTLE
S-CLOCK
PULSE GEN.
S-ENABLE
HEADPHONE L.R
MAIN L or L+C
TDA7265
MAIN R or R+C
Block Diagram
9-1
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