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MPEG BOARD UD705 ZR36748 (VIDEO DAC ENCODER)
Pin No.
1
2
3
4
5
6
7
SSCRRO/CPC1011
8
SSCRRO/CPC1010
9 to 14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
SSCRXD/GPC108
50
51
SSCRXD/GPC109
52
53 to 55
RAMADD0 to 3
Pin Name
I/O
VDDP
—
DUPRD
—
BOOTSEL2
—
GPCI014
I
GPCI013
—
GPCI012
—
I
I
ATDD5 to 10
I
GNDP
—
ATDD4
I
VDDP
—
ATDD11
I
ATDD3
I
ATDD12
I
ATDD2
I
ATDD13
I
ATDD1
I
ATDD14
—
ATDD0
I
ATDD15
O
ATIOW
O
VDDC
—
ATIOR
O
GNDP
—
ATIORD
I
ATIOFFRO
—
GNDP
—
ATDA2
O
VDDP
—
ATDA1
I
ATDA0
I
ATCS1
I
ATCS0
I
BOOTSEL1
—
GPCI01
I
SSCSRO
I
GPC103
I
GCP104
—
GCP105
O
GCP106
O
GCP107
I
VDDP
—
I
GNDP
—
I
VDDP
—
O
Published in Heiloo Holland
Power supply terminal (+3.3V)
Not used
Not used
LSI RST signal input from the AV decoder
Not used
Not used
Chip enable signal input from the system controller
Clock signal input from the system controller
DVD (RF) signal input from the AV decoder
Ground terminal
DVD (RF) signal input from the AV decoder
Power supply terminal (+3.3V)
DVD (RF) signal input from the AV decoder
DRFO signal input from the AV decoder
DACK signal input from the AV decoder
DFFR signal input from the AV decoder
DBGN signal input from the AV decoder
DCLK signal input from the AV decoder
Not used
DMUTE signal input
DVD tray open signal output
DVD tray close signal output
Power supply terminal (+1.8V)
LMTSW signal output from the AV decoder
Ground terminal
RDY signal input
Not used
Ground terminal
RF servo gain up signal output
Power supply terminal (+3.3V)
C2F signal input from the AV decoder
LRCK signal input from the AV decoder
BCK signal input from the AV decoder
CD DATA signal input from the AV decoder
Not used
INTDET signal input from the AV decoder
Not used in this set. Fixed at ("L").
WRO signal input from the AV decoder
Not used
Serial data output to the audio DAC
Serial data clock output to the audio DAC
SPDFG signal input
Power supply terminal (+3.3V)
Data signal input from the system controller
Ground terminal
Data signal input from the system controller
Power supply terminal (+3.3V)
Address bus to the D-RAM
Description
HCD-DV2D
07/11/2016
47