Chapter 6. Block Diagram/Wiring Diagram System Block Diagram - Sharp LC-32DH57RU, LC-32DH57S Service Manual

2. Detailed ICs Information
2.1. IC1301 (VHiAK4341ED-1Y)
2.1.1 Block Diagram
2.1.2 Pin Connections and short description
Pin No. Pin Name I/O
1 MCLK I
2 BICK I
3 SDTI I
4 LRCK I
5 RDN I
6 SMUTE I
7 ACKS I
8 DIF I
9 DEM I
10 AOUTR O
11 AOUTL O
12 HVDD I
13 VSS —
14 VDD —
15 VCOM O
16 GAIN I
Master clock input pin. An external TTL clock should be input on this pin.
Audio serial data clock pin.
Audio serial data input pin.
L/R clock pin.
Power-down mode pin.
When at "L", the AK4341 is in the power-down mode, held in reset and AOUTL/R are held in VCOM.
The AK4341 must be reset once upon power-up.
Soft mute pin in parallel control mode.
"H": Enable, "L": Disable
Auto setting mode pin.
"L": Manual setting mode, "H": Auto setting mode.
Audio data interface format pin.
"L": 24bit MSB justified, "H"; I2S.
De-emphasis enable pin.
"H": Enable, "L": Disable
Rch analog output pin.
When PDN pin = "L", outputs VCOM voltage.
Lch analog output pin.
When PDN pin = "L", outputs VCOM voltage.
Output buffer power supply pin.
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic cap.
Ground pin.
DAC power supply pin.
DAC common voltage pin.
Normally connected to VSS with a 10µF electrolytic cap.
Outputs VCOM VDD voltage either PDN pin = "L" or "H".
Gain control pin.
"H": +6dB, "L": 0dB, open: +12dB.
When PDN = "H", the gain pin is connected to VDD and VSS with 50kΩ resister and held to VDD/2 when open.
When PDN = "L", connected to VSS with 50kΩ resister.
Pin Function
5 – 3
LC-32DH57E/RU/S