JVC XV-S40BK Service Manual page 31

MN102L62GGY (IC401) : Unit CPU
Pin function
Symbol I/O
Pin No.
1 Micon wait signal input
I
WAIT
2 Read enable
O
RE
3 Spindle muting output to IC251
O
SPMUTE
4 Write enable
O
WEN
5 HD Type selection
O
HDTYPE
6 Chip select for ODC
O
CS1
7 Chip select for ZIVA
O
CS2
8 Chip select for outer ROM
O
CS3
9 Driver mute
O
DRVMUTE
10 Short brake terminal
O
SBRK
LSI reset
11 O
LSIRST
Bus selection input
12 I
WORD
Address bus 0 for CPU
13 O
A0
Address bus 1 for CPU
14
A1 O
Address bus 2 for CPU
15
A2 O
Address bus 3 for CPU
16
A3 O
17 Power supply
VDD -
18 Non connect
SYSCLK -
19 Ground
VSS -
20 Not use (Connect to vss)
XI -
21 Non connect
XO -
22 Power supply
VDD -
23 Clock signal input(13.5MHz)
OSCI I
24 Clock signal output(13.5MHz)
OSCO O
25 CPU Mode selection input
MODE I
26 Address bus 4 for CPU
A4 O
27 Address bus 5 for CPU
A5 O
28 Address bus 6 for CPU
A6 O
29 Address bus 7 for CPU
A7 O
30 Address bus 8 for CPU
A8 O
31 Address bus 9 for CPU
A9 O
32 Address bus 10 for CPU
A10 O
33 Address bus 11 for CPU
A11 O
34 Power supply
VDD -
35 Address bus 12 for CPU
A12 O
36 Address bus 13 for CPU
A13 O
37 Address bus 14 for CPU
A14 O
38 Address bus 15 for CPU
A15 O
39 Address bus 16 for CPU
A16 O
40 Address bus 17 for CPU
A17 O
41 Address bus 18 for CPU
A18 O
42 Address bus 19 for CPU
A19 O
43 Ground
VSS -
44 Address bus 20 for CPU
A20 O
45 TX Select
TXSEL O
46 Detection switch of traverse
TRVSW I
inside
47 Connect to TP408
HUGUP -
48 HFM Control output to Q103
HFMON O
49 Connect to pick-up
HAGUP O
50 Connect to TP407
- -
Function
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
XV-S40BK/XV-S42SL/XV-S45GD
Symbol I/O
Connect to TP406
-
-
Connect to TP405
-
-
Connect to TP404
-
P85/TM5IO
Power supply
-
VDD
Connect to TP403
-
-
Serial enable signal for FEP
O
FEPEN
Standby signal for FEP
O
SLEEP
Connect to TP402
-
-
Communication busy
I
BUSY
Communication request
O
REQ
Ground
-
VSS
EEPROM chip select
O
EPCS
EEPROM clock
O
EPSK
EEPROM data input
I
EPDI
EEPROM data output
O
EPDO
Power supply
-
VDD
Communication clock
SCLKO O
Communication input data
S2UDT I
Communication output data
U2SDT O
Clock for ADSC serial
CPSCK O
Not use (Pull down)
P74/SBI1 I
ADSC serial data output
SDOUT O
Not use (Pull up)
- I
Not use (Pull up)
- I
NMI Terminal
NMI I
Interrupt input of ADSC
ADSCIRQ I
Interrupt input of ODC
ODCIRQ I
Interrupt input of ZIVA
DECIRQ I
Not use (Pull down)
CSSIRQ I
Interruption of system control
ODCIRQ2 I
Address data selection input
ADSEP I
Reset input
RST I
Power supply
VDD -
Test signal 1 input
TEST1 I
Test signal 2 input
TEST2 I
Test signal 3 input
TEST3 I
Test signal 4 input
TEST4 I
Test signal 5 input
TEST5 I
Test signal 6 input
TEST6 I
Test signal 7 input
TEST7 I
Test signal 8 input
TEST8 I
Ground
VSS -
Data bus 0 of CPU
D0 I/O
Data bus 1 of CPU
D1 I/O
Data bus 2 of CPU
D2 I/O
Data bus 3 of CPU
D3 I/O
Data bus 4 of CPU
D4 I/O
Data bus 5 of CPU
D5 I/O
Data bus 6 of CPU
D6 I/O
Data bus 7 of CPU
D7 I/O
XV-S30BK/XV-E100SL
Function
1-31