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IC62 : TC9462F (DIGITAL SIGNAL PROCESSOR)
BLOCK DIAGRAM
80
79
78
DVSR
81
RO
82
DVDD
83
DVR
84
LO
85
DVSL
86
TEST1
87
88
TEST2
TEST3
89
BUS0
90
BUS1
91
BUS2
92
BUS3
93
VDD
94
VSS
95
BUCK
96
CCE
97
TEST4
98
TSMOD
99
RST
100
1
2
3
PIN FUNCTION
PIN No.
NAME
I/ O
FUNCTIONAL DESCRIPTION
1
TEST0
-
Test mode terminal. Normally, keep at open.
Playback speed mode flag output terminal.
2
HSO
O
UHSO
HSO
H
H
H
L
UHSO
L
H
3
O
L
L
Subcode Q data emphasis flag output terminal.
Emphasis ON at "H" level and OFF at "L" level.
4
EMPH
O
The output polarity can invert by command.
Channel clock output terminal. (44.1 kHz)
5
LRCK
O
L-ch at "L" level and R-ch at "H" level.
The output polarity can invert by command.
Digital GND terminal.
6
V
-
SS
Bit clock output terminal. (1.4112 MHz)
7
BCK
O
Audio data output terminal.
8
AOUT
O
Digital data output terminal.
9
DOUT
O
Buffer memory over signal output terminal.
10
MBOV
O
Over at "H" level.
Correction flag output terminal.
At "H " level, AOUT output is made to correction
11
IPF
O
impossibility by C
correction processing.
2
Subcode Q data CRCC check adjusting result output
12
SBOK
O
terminal. The adjusting result is OK at "H" level.
Subcode P~W data readout clock input/output
13
CLCK
I/O
terminal. This terminal can select by command bit.
Digital power supply voltage terminal.
14
V
-
DD
Digital GND terminal.
15
V
-
SS
Subcode P~W data output terminal.
16
DATA
O
Playback frame sync signal output terminal.
17
SFSY
O
Subcode block sync signal output terminal.
18
SBSY
O
Processor status signal readout clock output terminal.
19
SPCK
O
Processor status signal output terminal.
20
SPDA
O
Correction frame clock output terminal. (7.35 kHz)
21
COFS
O
Internal signal (DSP internal flag and PLL clock) output
22
MONIT
O
terminal. Selected by command.
Digital power supply voltage terminal.
23
V
-
DD
Test input/output terminal. Normally, keep at "L" level.
24
TESIO0
I
PLL double reference voltage supply terminal.
25
P2V
-
REF
2/4 times speed at "VREF" voltage.
26
HSSW
O
1 bit DA converter zero detect flag output terminal.
27
ZDET
O
Phase difference signal output terminal of EFM signal
28
PDO
O
and PLCK signal.
TMAX detection result output terminal. Selected by
29
TMAXS
O
command bit (TMPS).
TMAX detection result output terminal. Selected by
command bit (TMPS).
30
TMAX
O
DIFFERENCE RESULT
Longer than fixed ferq.
Shorter than fixed freq.
Within the fixed freq.
All manuals and user guides at all-guides.com
77
76
75
74
73
72
71
70
69
68
Address
circuit
Digital out
4
5
6
7
8
9
10
11
12
13
REMARKS
With pull-up resistor.
PLAYBACK SPEED
-
Normal
2 times
4 times
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2-state output (PV
,HiZ)
REF
-
3-state output
(P2V
,PV
V
)
REF
REF,
SS
-
3-state output
TMAX OUTPUT
(P2V
,HiZ
V
)
REF
,
SS
"P2V
"
REF
"V
"
SS
"HiZ"
67
66
65
64
63
62
61
60
59
58
Servo
PWM
control
ROM
Digital equalizer
Automatic adjustment
RAM
circuit
CLV servo
Synchronous
guarantee
EFM decode
Sub code
Status
decoder
14
15
16
17
18
19
20
21
22
23
PIN No.
NAME
I/ O
FUNCTIONAL DESCRIPTION
31
LPFN
I
LPF amplifier inverting input terminal for PLL.
LPF amplifier output terminal for PLL.
32
LPFO
O
33
PV
-
PLL reference voltage supply terminal.
REF
VCO center frequency reference level terminal.
34
VCOREF
I
Normally, keep at "PV
VCOF
35
O
VCO filter terminal.
AV
Analog GND terminal.
36
SS
-
37
SLCO
O
Data slice level output terminal.
38
RFI
I
RF signal input terminal.
Analog power supply voltage terminal.
39
AV
-
DD
40
RFCT
I
RFRP signal center level input terminal.
RFRP zero cross input terminal.
41
RFZI
I
42
RFRP
I
RF ripple signal input terminal.
43
FEI
I
Focus error signal input terminal.
Sub-beam adder signal input terminal.
44
SBAD
I
45
TSIN
I
Test input terminal. Normally, keep at "V
Tracking error signal input terminal.
46
TEI
I
Track in at tracking servo on.
47
TEZI
I
Trcaking error zero cross input terminal.
Focus servo equalizer output terminal.
48
FOO
O
49
TRO
O
Tracking servo equalizer output terminal.
50
V
-
Analog reference voltage supply terminal.
REF
RF amplitude adjustment control signal output terminal.
51
RFGC
O
52
TEBC
O
Tracking balance control signal output terminal.
Feed equalizer output terminal.
53
TEBC
O
Speed error signal or feed search equalizer output
54
TEBC
O
terminal.
Disk equalizer output terminal. (PWM carrier = 88.2 kHz
55
DMO
O
for DSP, Synchronize to PXO)
56
2V
-
Analog double reference voltage supply terminal.
REF
APC circuit ON/OFF indication signal output terminal.
57
SEL
O
At the laser on time, UHF = L at "HiZ" level and
UHF = H at "H" level.
Extemal flag output terminal for internal signal.
58
FLGA
O
Can select signal from TEZC, FOON, FOK and RFZC by
command.
Extemal flag output terminal for internal signal.
59
FLGB
O
Can select signal from DECT, FOON, FMON and RFZC
by command.
Extemal flag output terminal for internal signal.
60
FLGC
O
Can select signal from TRON, TRSR, FOK and SRCH by
command.
Extemal flag output terminal for internal signal.
61
FLGD
O
Can select signal from TRON, DMON, HYS and SHC by
command.
62
V
-
Digital power supply voltage terminal.
DD
Digital GND terminal.
63
V
-
SS
General I/O terminal. Can change over input port or
64
IO0
output port by command. At the input mode time can
65
IO1
I/O
readout a state of terminal (H/L) by read command. At
66
IO2
the output mode time can control a state of terminal
67
IO3
(H/L/HiZ) by command.
18
57
56
55
54
53
52
51
VREF
50
49
TRO
D / A
FOO
48
47
TEZI
TEI
46
45
TSIN
44
SBAD
43
EF1
RFRP
42
41
RFZI
RFCT
40
39
AVDD
38
RF1
SLCO
37
AVSS
36
35
VCOF
VCOREF
34
VCO
33
PVREF
32
LPFO
31
LPFN
24
25
26
27
28
29
30
REMARKS
Analog input.
Analog output.
-
-
" level.
REF
Analog output.
-
Analog output.
Analog input (Zin : selected by command)
-
Analog input (Zin : 50k
Analog input.
Analog input.
Analog input.
Analog input.
Analog input.
" level.
REF
Analog input.
Analog input (Zin : 10k
Analog output (2V
REF
-
3-state PWM signal output.
(2V
, V
, V
)
REF
REF
SS
(PWM carrier = 88.2 kHz)
3-state PWM signal
output.(2VREF, VREF, VSS)
-
-
-
-
-
-
-
-
-
)
)
~AV
)
SS
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