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MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
I2C0/1_DATA
JX710
0R
BX100
80-WAY
I2C0_DATA
1
2
3
4
I2C1_DATA
5
6
I2C2_DATA
7
8
PCMDATA0
9
10
LINE_O/P_L
11
12
DVI_L_IN
13
14
15
16
DVI_R_IN
17
18
CR_L_IN
19
20
CR_R_IN
21
22
VGA_L_IN
23
24
25
26
VGA_R_IN
27
28
29
30
AV3/F_CVBS_IN
31
32
AV3/F_CHROMA_IN
33
34
Y_AV_IN
35
36
C_AV_IN
37
38
SL_TUNER_CVBS
39
40
41
42
MA_TUNER_CVBS
43
44
45
46
AV2_BLUE
47
48
AV2_PIN8_IN
49
50
AV2_GREEN
AV2_RED/C_IN
51
52
AV2_PIN16
53
54
55
56
57
58
CVBS_AV2_OUT2
59
60
AV2_CVBS/Y_IN
61
62
AV1_BLUE
63
64
AV1_PIN8_IN
65
66
AV1_GREEN
67
68
AV1_RED/C_IN
69
70
AV1_PIN16
71
72
73
74
AV1_CVBS/Y_IN
75
76
CVBSOUT_AV1_CTRL
77
78
COMP_L_IN
79
80
COMP_R_IN
DGND
DIGITAL INTERFACE
SCH IFC230E AV BOARD
EFC031-IFC130-IFC230
First issue 12/05
I2C0/1_CLK
JX713
0R
I2C0_CLK
I2C1_CLK
I2C2_CLK
LRCLK
BCLK
LINE_O/P_R
MASTER_MUTE
RESET_AUDIO
AUDIO_STBY
YC_SEL_CTRL2
YC_SEL_CTRL1
CVBSIN_AV3_CTRL
CVBSOUT_AV2_CTRL
JX701
0R
JX702
0R
JX703
0R
JX704
0R
JX705
0R
JX706
0R
DGND
AGND
DGND
!
FP101
#
RP100
T315MA 125V
12R
3W
#
TRUTH TABLE
COMP
37LB330B5 42LB330B5 46LB330B5
RP100
12R 3W
0R Wire
RP101
12R 3W
0R Wire
JP111
JP110
0R
0R
BP100
LP111
14
+12V
VOLTAGE REGULATOR
13
+6V5
RA286
RA285
12
SCH IFC230E AV BOARD
2K2
2K2
11
+12V_GND
10
AGND
+12V_UA
9
+12V_UA
+12V_UA
8
7
LP110
6
+6.5V
+6V5
+24V_GND
5
4
3
2
+24V
+24V
1
JP001
+24V_GND
0R
+24V_GND
+12V_GND
JP00 2
0R
JP003
0R
+12V_GND
AGND
IP103
#
RP101
LD1117DT
12R
3W
IN
OUT
IN
OUT
RP105
GND
560R
ICS
CP104
CP108
CP109
220N
220UF
220N
CP105
16V
0R Wire
16V
CP118
16V
100UF
RP106
10U
0R Wire
16V
16V
3K9
AGND
IP104
KF80BDT
1
3
IN
OUT
GND
2
CP110
CP107
CP106
220N
100UF
220N
16V
16V
16V
GND
RS277
5K1
IP101
LD1117DT33
RS278
+24V_1
5K1
IN
OUT
IN
OUT
RS279
CP101
GND
CP112
CP102
5K1
100UF
100UF
220N
16V
16V
GND
IP106
LF50CDT
1
3
IN
OUT
GND
2
CP131
CP130
CP115
220N
220N
220UF
16V
16V
16V
AGND
GND
10V
8V
3V3
CP111
220N
5V
CP116
100UF
16V
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