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Note: Each key has two contacts,
the first conatct (1) and second contact (2).
NOMENCLATURE OF KEYS
C#2
D#2
F#2
G#2
A#2
C#3
C2 D2
E2
F2
G2 A2
B2
C3 D3
POWER SUPPLY CIRCUIT
The power supply circuit generates five voltages as shown in the following table. VDD voltage is always
generated. The others are controlled by APO signal from the CPU.
N
a
m
e
V
l o
a t
g
e
V
D
D
+
5
V
C
D
V
D
D
+
5
V
L
A
V
D
D
+
5
V
D
L
V
D
D
+
5
6 .
V
L
V
C
C
+
9
V
P
RESET CIRCUIT
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU. The
CPU then initializes its internal circuit, and clears the working storage RAM.
When the power switch is pressed, the CPU receives a low pulse of POWER signal. The CPU sends APO
signal to the power supply circuit, also sends a reset signal to the DSP.
Battery set
VDD
Reset IC
IC1
RN5VD40AA
From power switch
D#3
F#3 G#3 A#3
C#4 D#4
E3
F3
G3 A3
B3 C4
D4 E4
P
, U
R
e
s
e
I t
, C
D
S
, P
S
o
u
n
C
D
r d
v i
e
, r
P
o
w
r e
a j
c
, k
S
u
s
A
, C
F
t l i
r e
C
D
i d
v r
r e
o
w
r e
a
m
p
f i l
e i
, r
P
l i
t o
a l
m
p
VDD
RESET
CPU
LSI1
UPD913GF-3BA
SCKO
POWER
NMI
Key
Second contact (2)
F#4 G#4 A#4
C#5 D#5
F#5 G#5 A#5
F4
G4
A4
B4 C5 D5
E5
F5
G5
F
r o
o
p
r e
t a
o i
n
f o
d
s
o
u
c r
e
R
O
M
,
W
o
k r
n i
g
s
a t
n i
a j
c
, k
M
I
I D
a j
k c
Reset signal
PLE
APO
To power supply circuit
— 5 —
First contact (1)
D#6
F#6
G#6
A#6
C#6
A5
B5
C6
D6
E6
F6
G6
A6
o t
a r
g
e
R
A
M
,
f E
e f
t c
R
A
M
VDD
DSP
LSI2
HG51B277FB-1
FI
KC
SI
B6
C7
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