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PRODUCT USER GUIDE
IO Name
CR Value Default*
0000
0001 *
0010
0011
SDIO_DAT3
0100
0101
0110
0111
0000
0001 *
0010
0011
GPIO_B_0
0100
0101
0110
0111
0000
0001 *
0010
0011
GPIO_B_1
0100
0101
0110
0111
0000
0001 *
0010
0011
GPIO_B_2
0100
0101
0110
0111
0000
0001 *
0010
0011
GPIO_B_3
0100
0101
0110
0111
0000
0001 *
0010
0011
GPIO_B_5
0100
0101
0110
0111
Name
Dir
GPIO[11]
I/O
SDIO_DAT3
I/O
MSDC0_DAT3
I/O
I2SO_DAT0
O
UART0_TX
O
DEBUG_5
O
I2C0_SDA
I
CM33_GPIO_EINT3
I
GPIO[12]
I/O
CONN_BGF_UART0_TXD
O
MSDC0_RST
O
CONN_BT_TXD
O
WIFI_TXD
O
DEBUG_6
O
ANT_SEL3
O
CM33_GPIO_EINT4
I
GPIO[13]
I/O
USB_IDDIG
I
SPIM1_SCK
O
I2SO_BCK
O
UART1_RX
I
DEBUG_7
O
ANT_SEL4
O
CM33_GPIO_EINT5
I
GPIO[14]
I/O
USB_DRV_VBUS
O
SPIM1_MOSI
O
I2SO_LRCK
O
DEBUG_8
O
ANT_SEL5
O
CM33_GPIO_EINT6
I
GPIO[15]
I/O
USB_OC
I
SPIM1_MISO
I
I2SO_MCK
O
I2SIN_MCK
O
DEBUG_9
O
ANT_SEL6
O
CM33_GPIO_EINT7
I
GPIO[17]
I/O
CONN_BGF_UART0_RXD
I
UART0_RX
I
TDMIN_MCLK
I
DMIC_CLK0
O
DEBUG_11
O
ANT_SEL8
O
CM33_GPIO_EINT9
I
www.acsip.com.tw
Default
Dir
PU/PD
GPIO 11
SDIO Data[3]
I2SO Data
I
PU
UART0 TX
Debug signal
I2C0 Data
CA33 EINT3
GPIO 12
MSDC0 reset
O
PU
Debug signal
Antenna Select 3
CA33 EINT4
GPIO 13
USB OTG ID pin
SPIM1 (Master) Clock
I2SO BCK
I
PU
UART1 RX
Antenna Select 4
CA33 EINT5
GPIO 14
USB OTG host mode
driving enable output
SPI1 (Master) Output
I2SO LRCK
O
PD
Debug signal
Antenna Select 5
CA33 EINT6
GPIO 15
USB Host mode over-
current input notify
SPI1 (Master) Input
I2STX MCLK
I
PD
I2SRX MCK
Debug signal
Antenna Select 6
CA33 EINT7
GPIO 17
UART0 RX
I
PU
DMIC CLK0
Debug signal
Antenna Select 8
CA33 EINT9
Product Name
Version
Doc No
Date
Page
Description
EK-AI7933CLD
A
912-13903
2022/04/29
19 /26
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