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Philips Semiconductors
Low power audio DAC
14.3
Timing
V
= V
= 1.8 to 3.6 V; T
DDD
DDA
unless otherwise specified; note 1.
SYMBOL
PARAMETER
System clock timing (see Fig.6)
T
system clock cycle time
sys
t
system clock HIGH time
CWH
t
system clock LOW time
CWL
Reset timing
t
reset time
reset
Serial interface timing (see Fig.7)
f
bit clock frequency
BCK
t
bit clock HIGH time
BCKH
t
bit clock LOW time
BCKL
t
rise time
r
t
fall time
f
t
set-up time data input
su(DATAI)
t
hold time data input
h(DATAI)
t
set-up time word select
su(WS)
t
hold time word select
h(WS)
Note
1. The typical value of the timing is specified at f
2002 May 22
= 20 to +85 C; R
amb
L
f
= 256f
sys
f
= 384f
sys
f
= 512f
sys
f
< 19.2 MHz
sys
f
19.2 MHz
sys
f
< 19.2 MHz
sys
f
19.2 MHz
sys
= 44.1 kHz (sampling frequency).
s
= 5 k ; all voltages with respect to ground (pins V
CONDITIONS
s
s
s
14
Product specification
UDA1334BT
SSA
MIN.
TYP.
MAX.
35
88
780
23
59
520
17
44
390
0.3T
0.7T
sys
sys
0.4T
0.6T
sys
sys
0.3T
0.7T
sys
sys
0.4T
0.6T
sys
sys
1
64f
s
50
50
20
20
20
0
20
10
and V
);
SSD
UNIT
ns
ns
ns
ns
ns
ns
ns
s
Hz
ns
ns
ns
ns
ns
ns
ns
ns
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