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Philips Semiconductors
Low power audio DAC
SYMBOL
PARAMETER
I
digital supply current
DDD
Digital input pins; note 2
V
HIGH-level input voltage
IH
V
LOW-level input voltage
IL
I
input leakage current
LI
C
input capacitance
i
3-level input: pin PCS
V
HIGH-level input voltage
IH
V
MID-level input voltage
IM
V
LOW-level input voltage
IL
DAC
V
reference voltage
ref(DAC)
R
output resistance on
o(ref)
pin V
ref(DAC)
I
maximum output current
o(max)
R
load resistance
L
C
load capacitance
L
Notes
1. All supply connections must be made to the same external power supply unit.
2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be
accepted, but levels from 3.3 V domain can be applied to the pins.
3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100
oscillations in the output operational amplifier.
2002 May 22
CONDITIONS
normal operating mode
at 2.0 V supply voltage
at 3.0 V supply voltage
Sleep mode;
at 2.0 V supply voltage
clock running
no clock running
Sleep mode;
at 3.0 V supply voltage
clock running
no clock running
at 2.0 V supply voltage
at 3.0 V supply voltage
at 2.0 V supply voltage
at 3.0 V supply voltage
with respect to V
SSA
(THD + N)/S < 0.1%;
R
= 800
L
note 3
12
MIN.
TYP.
1.4
2.1
250
20
375
30
1.3
2.0
0.5
0.5
0.9V
DDD
0.4V
DDD
0.5
0.45V
0.5V
DDA
DDA
25
1.6
3
must be used to prevent
Product specification
UDA1334BT
MAX.
UNIT
mA
mA
A
A
A
A
3.3
V
5.0
V
+0.5
V
+0.8
V
1
A
10
pF
V
+ 0.5
V
DDD
0.6V
V
DDD
+0.5
V
0.55V
V
DDA
k
mA
k
50
pF
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