Casio CTK-731 Service Manual page 8

MEMORY DEVICES
Each memory device has the following data.
CPU
Internal Memory
3
ROM 512 kbit
4
RAM 16 kbit
LSI9
DSP
LSI4
Working RAM
7
256 kbit
LSI5
RESET CIRCUIT
Battery set
VDD
RESET
PWSW
From power switch
Initial reset
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU.
When the power switch is pressed, the CPU receives a low pulse of POWER signal. The CPU first raises
APO signal to +5 V to generate DVDD voltage, then raises RESET signal to +5 V. During this period the
DSP, the key controller and FDD controller LSIs initialize their internal circuits.
1 RAM1 :
RAM1
S-RAM for operation program, Register, Pattern, Song
1
and SMF data from FDD. (Lower part of data bus)
1 Mbit
LSI7
2 RAM2 :
S-RAM for operation program, Register, Pattern, Song
RAM2
and SMF data from FDD. (Upper part of data bus)
2
3 Internal ROM of CPU :
1 Mbit
Main program data for system operation
LSI8
4 Internal RAM of CPU :
ROM1
Work area for system operation
5
8 Mbit
5 ROM1 :
LSI2
Demo, Accompaniment data, Song, Pattern, Synth, Disk
mode
ROM2
6 ROM2 :
6
Sound Waveforms/Tone data Digital sound effect
32 Mbit
LSI3
7 Working RAM :
Work area for DSP
VDD
RESET
RES PB0
CPU
HD6433042SB51F
LSI9
APO
NMI PA7
— 7 —
DVDD
FDD Controller
HD63266F
LSI6
RESET
PW/SW ON
RESET
APO
DVDD
(5V)
Power Supply
Circuit
DVDD
DSP
HG51B155FD
LSI4
RESB
DVDD
RESB
Key Controller
TC190C020AF-001
LSI10
DVDD