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Pin
Mark
I/O
No.
Division
54
SMON3
O
55
SMON2
O
56
SMON1
O
57
SMON0
O
58
FSEQ
O
59
VP
O
60
FOK
O
61
DEFECT
O
62
UCLK
O
63
VDD1
I
64
VSS
—
65
VDD2
I
66
CL
I
67
CE
I
68
DI
I
69
DO
O
70
WRQ
O
71
INT
72
ADIPW0
I
73
RCUT
I
74
PCK
O
75
VCVDD
I
76
FR
I
Function
Monitor signal output
terminal (Not used, open)
Monitor signal output
terminal
Monitor signal output
terminal
Monitor signal output
terminal (Not used, open)
Not used, open
CLV servo clock judgement
output terminal (Not used,
open)
Focus OK signal output
terminal
Defect signal output
teminal (Not used, open)
4.2336MHz/8.4672MHz
output terminal (Not used,
open)
Powe supply terminal
GND terminal
Power supply terminal
CPU interface data clock
input terminal
CPU interface chip enable
signal input terminal
CPU interface data input
terminal
CPU interface data output
terminal
CPU interface interrupt
signal output terminal
Wobble signal input
terminal
Input terminal for test
(Connected to GND)
VCEC clock signal output
terminal
Power supply terminal for
VCEC
Bias resistor terminal of
VCEC osillation frequency
(Connected to power
supply through resistor)
28
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