Sony MCE-K700 Service Manual page 43

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Pin No. Pin Name
81 B/Cb0
82 B/Cb1
83 B/Cb2
84 B/Cb3
85 B/Cb4
86 B/Cb5
87 B/Cb6
88 B/Cb7
89 DCLK
90 V
DD
91 V
SS
92 HSYNC
93 VSYNC
FID
94
/FHREF
CBLNK
95
/FSC
96 CSYNC
97 XSGRST
98 CLK0O
99 DOUT
100 DATO
101 LRCO
102 BCKO
103 FSXI
104 V
DD
105 V
SS
106 XTL2O
107 XTL2I
108 V
DD
109 C2PO
110 LRCI
I/O
O
O
O
O Output pin of the B or Cb signal of the image data. MSB is B/Cb7. Synchronizes with
O DCLK.
O
O
O
Dot clock (DCLK) signal pin. The DCLK frequency is normally 13.5MHz. The DCLK can
I/O be input from this pin or can be made by frequency-dividing (1/integer) the clock input
from XTL0I.
– +5V power supply
– Ground
Horizontal sync signal pin. When using the built-in sync generator, a signal is made by
I/O frequency-dividing the dot clock (DCLK). Serves as the input when not using the built-in
sync generator.
Vertical sync signal pin. When using the built-in sync generator, a signal is made by fre-
I/O
quency-dividing the DCLK. Serves as the input when not using the built-in sync generator.
Field determination signal signal. Odd field correspond to H and even field correspond to
L. Serves as an output when the built-in sync generator is used, and as an input when not.
I/O
/ Signal obtained by frequency-dividing the clock input from XTL0I or XTLI. When the
/O
input clock is 8 fsc, it can be used as the horizontal sync signal phase comparison reference
signal.
Composite blanking signal pin. Serves as an output when the built-in sync generator is
I/O used, and as an input when not. / Signal obtained by frequency-dividing the clock input
/O
from XTL0I or XTLI. When the input clock is 8 fsc, it can be used as the fsc signal.
(Not used, open)
Composite sync signal pin. A signal is made by frequency-dividing the DCLK. Cannot be
O
input.
I Sync generator reset signal pin. The signal generator is initialized by setting this pin to 'L'.
Outputs the frequency-divided clock of the clock input to XTL0I. The frequency dividing
O
ratio can be selected from 1/2, 1/4, and 1/8.
O Digital output (Not used. open)
O Audio serial data output pin. Synchronizes with the clock input from FSXI.
O LR clock output pin. Outputs the clock input from the LRCI. (Not used. open)
O Bit clock output pin. Outputs the clock input from the BCKI. (Not used. open)
I Input 384fs (16.9344MHz) or 768fs (33.8688MHz).
– +5V power supply
– Ground
CD-ROM decoder, audio decoder master clock. Input a clock to the XTL21 or connect an
O
oscillator between XTL2I and XTL2O. The recommended frequency is 45 MHz. This clock
I is for the internal circuit. Does not synchronize with inputs and outputs.
– +5V power supply
I C2 pointer input
I LR clock input
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Function