Macronix MX25L4006E Manual

3v, 4m-bit [x 1/x 2] cmos serial flash memory

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MX25L4006E

3V, 4M-BIT [x 1/x 2]

CMOS SERIAL FLASH MEMORY

Key Features

• Hold Feature

• Low Power Consumption

• Auto Erase and Auto Program Algorithms

• Provides sequential read operation on whole chip

P/N: PM1576

REV. 1.6, OCT. 24, 2014

Table of Contents

Summary of Contents for Macronix MX25L4006E

Page 1 MX25L4006E MX25L4006E 3V, 4M-BIT [x 1/x 2] CMOS SERIAL FLASH MEMORY Key Features • Hold Feature • Low Power Consumption • Auto Erase and Auto Program Algorithms • Provides sequential read operation on whole chip P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 2: Table Of Contents
Table 6. Signature and Parameter Identification Data Values ................21 Table 7. Parameter Table (0): JEDEC Flash Parameter Tables ................. 22 Table 8. Parameter Table (1): Macronix Flash Parameter Tables ..............24 POWER-ON STATE ..............................26 ELECTRICAL SPECIFICATIONS ..........................27 Absolute Maximum Ratings ..........................
Page 3 MX25L4006E Figure 3. Maximum Negative Overshoot Waveform ..................27 Capacitance TA = 25°C, f = 1.0 MHz ........................27 Figure 4. Maximum Positive Overshoot Waveform .................... 27 Figure 5. Input Test Waveforms and Measurement Level .................. 28 Figure 6. Output Loading ............................ 28 Table 9.
Page 4: Features
MX25L4006E 4M-BIT [x 1/x 2] CMOS SERIAL FLASH FEATURES GENERAL • Supports Serial Peripheral Interface -- Mode 0 and Mode 3 • 4,194,304 x 1 bit structure or 2,097,152 x 2 bits (Dual Output mode) structure • 128 Equal Sectors with 4K byte each - Any Sector can be erased individually •...
Page 5: General Description
WIP bit. When the device is not in operation and CS# is high, it is put in standby mode. The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.
Page 6: Block Diagram
MX25L4006E BLOCK DIAGRAM Address Generator Memory Array Page Buffer Data SI/SIO0 Register Y-Decoder SO/SIO1 SRAM Buffer Sense CS#, Amplifier Mode State WP#, Logic Machine HOLD# Generator SCLK Clock Generator Output Buffer P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 7: Memory Organization
MX25L4006E MEMORY ORGANIZATION Table 1. Memory Organization Block Sector Address Range 07F000h 07FFFFh 070000h 070FFFh 06F000h 06FFFFh 060000h 060FFFh 05F000h 05FFFFh 050000h 050FFFh 04F000h 04FFFFh 040000h 040FFFh 03F000h 03FFFFh 030000h 030FFFh 02F000h 02FFFFh 020000h 020FFFh 01F000h 01FFFFh 010000h 010FFFh 00F000h...
Page 8: Device Operation
MX25L4006E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended op- eration. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge.
Page 9: Data Protection
MX25L4006E DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully.
Page 10: Hold Feature
MX25L4006E HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low).
Page 11 MX25L4006E During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will keep high impedance until Hold# pin goes high and SCLK goes low. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high.
Page 12 MX25L4006E Table 3. Command Definition WREN WRSR RDID RDSR Fast Read COMMAND WRDI READ (write (write status (read (read status (fast read (byte) (write disable) (read data) Enable) register) identification) register) data) 06 Hex 04 Hex 01 Hex 9F Hex...
Page 13: Command Description
MX25L4006E COMMAND DESCRIPTION (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in- struction setting the WEL bit.
Page 14: Read Status Register (Rdsr)
MX25L4006E (3) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress.
Page 15: Write Status Register (Wrsr)
MX25L4006E (4) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad- vance.
Page 16: Read Data Bytes (Read)
MX25L4006E (5) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction.
Page 17: Block Erase (Be)
MX25L4006E The sequence is shown as Figure The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Page 18: Deep Power-Down (Dp)
MX25L4006E The sequence is shown as Figure The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex- ecuted.
Page 19: Read Identification (Rdid)
(14) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID is as followings: 13(hex) for MX25L4006E.
Page 20: Read Sfdp Mode (Rdsfdp)
MX25L4006E (16) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors.
Page 21 Start from 01h 23:16 Number Parameter Table Length How many DWORDs in the 31:24 (in double word) Parameter table 07:00 First address of Macronix Flash Parameter Table Pointer (PTP) 15:08 Parameter table 23:16 Unused 31:24 P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 22 MX25L4006E Table 7. Parameter Table (0): JEDEC Flash Parameter Tables SFDP Table below is for MX25L4006EM1I-12G, MX25L4006EM2I-12G, MX25L4006EPI-12G, MX25L4006EZNI- 12G and MX25L4006EZUI-12G Add (h) DW Add Data (h/b) Data Description Comment (Byte) (Bit) (Note1) 00: Reserved, 01: 4KB erase, Block/Sector Erase sizes...
Page 23 MX25L4006E SFDP Table below is for MX25L4006EM1I-12G, MX25L4006EM2I-12G, MX25L4006EPI-12G, MX25L4006EZNI- 12G and MX25L4006EZUI-12G Add (h) DW Add Data (h/b) Data Description Comment (Byte) (Bit) (Note1) (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy 04:00 0 1000b states...
Page 24 MX25L4006E Table 8. Parameter Table (1): Macronix Flash Parameter Tables SFDP Table below is for MX25L4006EM1I-12G, MX25L4006EM2I-12G, MX25L4006EPI-12G, MX25L4006EZNI- 12G and MX25L4006EZUI-12G Add (h) DW Add Data (h/b) Data Description Comment (Byte) (Bit) (Note1) 2000h=2.000V 07:00 Vcc Supply Maximum Voltage 2700h=2.700V...
Page 25 Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix. P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 26: Power-On State
MX25L4006E POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct...
Page 27: Electrical Specifications
MX25L4006E ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings RATING VALUE Industrial (I) grade -40°C to 85°C Ambient Operating Temperature Storage Temperature -55°C to 125°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V Notes: 1.
Page 28 MX25L4006E Figure 5. Input Test Waveforms and Measurement Level Input timing reference level Output timing reference level 0.8VCC 0.7VCC Measurement 0.5VCC Level 0.3VCC 0.2VCC Note: Input pulse rise and fall time are <5ns Figure 6. Output Loading DEVICE UNDER 2.7K ohm +3.3V...
Page 29 MX25L4006E Table 9. DC Characteristics (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) Symbol Parameter Notes Min. Typ. Max. Units Test Conditions VCC = VCC Max Input Load Current ± 2 VIN = VCC or GND VCC = VCC Max Output Leakage Current ±...
Page 30 MX25L4006E Table 10. AC Characteristics (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) Symbol Alt. Parameter Min. Typ. Max. Unit Clock Frequency for the following instructions: fSCLK FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR...
Page 31 MX25L4006E Table 11. Power-Up Timing Symbol Parameter Min. Max. Unit tVSL(1) VCC(min) to CS# low Note: 1. The parameter is characterized only. Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
Page 32 MX25L4006E Timing Analysis Figure 7. Serial Input Timing tSHSL tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH High-Z Figure 8. Output Timing SCLK tCLQV tCLQV tSHQZ tCLQX ADDR.LSB IN P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 33 MX25L4006E Figure 9. Hold Timing tHLCH tHHCH tCHHL SCLK tCHHH tHLQZ tHHQX tCLHS tCLHH HOLD# * SI is "don't care" during HOLD operation. Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 tSHWL tWHSL SCLK High-Z P/N: PM1576...
Page 34 MX25L4006E Figure 11. Write Enable (WREN) Sequence (Command 06) SCLK Command High-Z Figure 12. Write Disable (WRDI) Sequence (Command 04) SCLK Command High-Z Figure 13. Read Status Register (RDSR) Sequence (Command 05) 9 10 11 12 13 14 15 SCLK...
Page 35 MX25L4006E Figure 14. Write Status Register (WRSR) Sequence (Command 01) 9 10 11 12 13 14 15 SCLK command Status Register In High-Z Figure 15. Read Data Bytes (READ) Sequence (Command 03) 9 10 28 29 30 31 32 33 34 35...
Page 36 MX25L4006E Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B) 9 10 28 29 30 31 SCLK Command 24 BIT ADDRESS 22 21 High-Z 32 33 34 36 37 38 39 40 41 42 43 44 45 46 SCLK...
Page 37 MX25L4006E Figure 18. Sector Erase (SE) Sequence (Command 20) 29 30 31 SCLK 24 Bit Address Command 23 22 Note: SE command is 20(hex). Figure 19. Block Erase (BE) Sequence (Command 52 or D8) 29 30 31 SCLK Command 24 Bit Address...
Page 38 MX25L4006E Figure 21. Page Program (PP) Sequence (Command 02) 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command 24-Bit Address Data Byte 1 22 21 43 44 45 46 47 48 49 50 52 53 54 55...
Page 39 MX25L4006E Figure 23. Read Electronic Signature (RES) Sequence (Command AB) 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command 3 Dummy Bytes RES2 22 21 Electronic Signature Out High-Z Deep Power-down Mode Stand-by Mode Figure 24.
Page 40 MX25L4006E Figure 25. Read Identification (RDID) Sequence (Command 9F) 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command Manufacturer Identification Device Identification High-Z 15 14 13 Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
Page 41 MX25L4006E Figure 27. Power-up Timing V CC V CC (max) Chip Selection is Not Allowed V CC (min) Device is fully accessible tVSL time P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 42 MX25L4006E OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in Figure 28 and Figure 29 are the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
Page 43 MX25L4006E Figure 29. Power-Down Sequence During power down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. SCLK P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 44 MX25L4006E ERASE AND PROGRAMMING PERFORMANCE Parameter Min. Typ. (1) Max. (2) Unit Write Status Register Cycle Time Sector erase Time Block erase Time Chip Erase Time Byte Program Time (via page program command) Page Program Time Erase/Program Cycle 100,000 cycles Note: 1.
Page 45 MX25L4006E ORDERING INFORMATION Clock Part No. Temperature Package Remark (MHz) 8-SOP MX25L4006EM1I-12G -40~85°C (150mil) 8-SOP MX25L4006EM2I-12G -40~85°C (200mil) 8-PDIP MX25L4006EPI-12G -40~85°C (300mil) 8-land WSON MX25L4006EZNI-12G -40~85°C (6x5mm) 8-USON MX25L4006EZUI-12G -40~85°C (2x3x0.6mm) P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 46 MX25L4006E PART NAME DESCRIPTION MX 25 4006E OPTION: G: RoHS Compliant and Halogen-free SPEED: 12: 86MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: ZN: WSON (0.8mm package height) M1: 150mil 8-SOP M2: 200mil 8-SOP P: 300mil 8-PDIP ZU: 8-USON (2x3x0.6mm) DENSITY &...
Page 47 MX25L4006E PACKAGE INFORMATION P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 48 MX25L4006E P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 49 MX25L4006E P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 50 MX25L4006E P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 51 MX25L4006E P/N: PM1576 REV. 1.6, OCT. 24, 2014...
Page 52 MX25L4006E REVISION HISTORY Revision No. Description Page Date 0.01 1. Modified "Initial Delivery State" description MAY/19/2010 2. Modified OTP Capable data from 1 to 0 3. Revised Vcc Supply Minimum Voltage Address Bits 4. Changed wording from DMC to SFDP P4,8,11,19 5.
Page 53 In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom.