Related Manuals for Open QCT F06S
Summary of Contents for Open QCT F06S
- Page 1 QCT F06S/ F06T 19” 2U 4Node/2Node System “Carmel” Revision 0.1 2016/1/28 Contributed by: Alan Chang, Quanta Computer Inc. Quanta Confidential...
- Page 2 F06S/F06T 2U System Contribution Revision History: Revision Date Description 2016-1-28 Release for Open Compute Project...
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Page 3: Table Of Contents
F06S/F06T 2U System Contribution Table of Contents 1 INTRODUCTION ............................4 2 PRODUCT ARCHITECTURE OVERVIEW ..................... 7 F06S 2U4N System Produt Features ........................ 7 2.1.1 Product Features ............................7 2.1.2 System Block Diagram ..........................8 F06T 2U2N System Produt Features ........................ 9 2.2.1 Product Features ............................ - Page 4 F06S/F06T 2U System Contribution 3.13 TPM ................................27 3.14 Serial port ..............................27 3.15 FANs ................................27 3.16 Jumper Definition ............................27 3.17 Debug header Information .......................... 29 3.17.1 XDP Support ............................29 3.17.2 SMB Debug Header (JP7) ........................29 3.17.3 BMC Debug Header (J1 and J10) ......................
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Page 5: Introduction
F06S/F06T 2U System Contribution 1 INTRODUCTION Both F06S and F06T (family code name Carmel) are 2RU height systems with OCP compliant 2P server board for standard 19” EIA rack. F06S is a 2U4N System with four hot-pluggable motherboard Sleds while F06T is a 2U2N System with two hot-pluggable motherboard Sleds. - Page 6 F06S/F06T 2U System Contribution http://www.opencompute.org/wiki/Motherboard/SpecsAndDesigns ), and it connects with SFP+ connectors of OCP mezzanine v1 card or RJ45 connector of Intel I210 LOM. The BMC (Baseboard Management Controller) is used to manage the sled itself which supports both in-band management and out-of-band management through the sideband control of Ethernet LAN.
- Page 7 F06S/F06T 2U System Contribution The figure below illustrates the functional block diagram of Facebook Server Intel motherboard Figure 1-4 Facebook Server Intel motherboard functional Block Diagram (quoted from Facebook Server Intel Next Generation Xeon motherboard v3.1, http://www.opencompute.org/wiki/Motherboard/SpecsAndDesigns The major differences between F06 OCP motherboard and Facebook Server Intel motherboard is as table 1-1 shown.
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Page 8: Product Architecture Overview
F06S/F06T 2U System Contribution 2 PRODUCT ARCHITECTURE OVERVIEW 2.1 F06S 2U4N System Produt Features 2.1.1 Product Features F06S 2U4N System’s ingredients and features are shown as follows. Item Features Form Factor 2U Chassis 31.1"x17.48"x3.44"(789.94 x 444 x 87.5mm) [LxW xH] Baseboard size / Quantity 20”... -
Page 9: System Block Diagram
F06S/F06T 2U System Contribution Power-Supply (2) 1600W high efficiency PSU, 220VAC 50/60Hz Chassis 2U chassis in 19” EIA rack Table 2-1 F06S 2U4N System Feature List 2.1.2 System Block Diagram Figure 2-1 F06S 2U4N System Block diagram... -
Page 10: F06T 2U2N System Produt Features
F06S/F06T 2U System Contribution 2.2 F06T 2U2N System Produt Features 2.2.1 Product Features F06T 2U2N System’s ingredients and features are shown as follows. Board Name F06T 2U2N System Form Factor 2U Chassis (Carmel Chassis) 31.1"x17.48"x3.44"(789.94 x 444 x 87.5mm) [LxW xH] Baseboard size / Quantity 20”... -
Page 11: System Block Diagram
F06S/F06T 2U System Contribution 2.2.2 System Block Diagram Figure 2-2 F06T 2U2N System Block diagram... -
Page 12: Related Board Placement
F06S/F06T 2U System Contribution 2.3 Related Board Placement 2.3.1 Motherboard Placement Figure 2-3 F06 OCP motherboard key part placement. Item Ref Designator / Silkscreen @PCB Description J1 / null Debug port U4 / USB USB 3.0 connector J6 / MEZZ CONN OCP Mezzanine v1 connector J12 / TPM TPM connector... -
Page 13: Interposer Board Placement
F06S/F06T 2U System Contribution J11 / MINISAS2 Mini-SAS connector J9 / MINISAS1 Mini-SAS connector J5 / SATA SATA connector Table 2-2 F06 OCP motherboard key part location list 2.3.2 Interposer Board Placement Figure 2-4 Interposer board key part placement Item Ref Designator / Silkscreen @PCB Description JP2 / CONN GUIDE... -
Page 14: Related Board Dimension
F06S/F06T 2U System Contribution 2.4 Related Board Dimension 2.4.1 Sled Dimension F06S Sled related dimension is 537.86mm (L, 21.17 “) x 173.75mm (W, 6.84”) x 40.5mm (H, 1.59”). Figure 2-5 F06S Sled dimension F06T Sled related dimension is 537.86mm (L, 21.17 “) x 173.75mm (W, 6.84”) x 81.5mm (H, 3.2”). Figure 2-6 F06T Sled dimension... -
Page 15: Motherboard Dimension
F06S/F06T 2U System Contribution 2.4.2 Motherboard Dimension The Motherboard related dimension is 508mm (L, 20 “) x 165mm (W, 6.5”). Figure 2-7 F06 OCP motherboard dimension 2.4.3 Interposer Board Dimension The Interposer board related dimension is 162mm (L, 6.38 “) x 60mm (W, 2.37”) Figure 2-8 Interposer board dimension... -
Page 16: Product Features
F06S/F06T 2U System Contribution 3 PRODUCT FEATURES 3.1 Processor The processor of Grantley platform is Xeon E5-2600 v3 and v4 (socket LGA2011 R3), the processor has internal voltage regulator (IVR). The key features are as shown below: Up to 18 cores (E5-2600 v3), 22 cores (E5-2600 v4) Up to 145W TDP Up to 10 x 4 PCIe Gen3 Support 4 channels DDR4 RDIMM/LRDIMM (total 16 DIMMs) -
Page 17: Dimm Nomenclature
F06S/F06T 2U System Contribution 3.2.1 DIMM Nomenclature DIMMs are organized into physical slots on DDR4 memory channels that belong to processor sockets. The memory channels from Socket 0 (CPU-0) are identified as Channel A0~A7. The memory channels from Socket 1 (CPU-1) are identified as Channel B0~B7. -
Page 18: Bmc
F06S/F06T 2U System Contribution 3.4 BMC The Board Management Controller of F06 OCP motherboard is adopting ASPEED AST1250 that is a highly integrated single-chip solution, integrating several devices typically found on servers. 3.5 Clocks The Grantley platform has three different clock architectures, external clock architecture (exCLK), integrated system clock (isCLK) architecture and hybrid architecture. -
Page 19: Usb
F06S/F06T 2U System Contribution 3.7 USB The C610 (PCH) supports total 14 USB ports, 6 USB 2.0 ports and 8 USB 3.0 ports. The USB port distribution is as follows: ASPEED BMC AST1250 occupies 2 USB 2.0 ports (one 1.1 and one 2.0-this one is reserved for AST2400, AST1250 won’t use USB2.0 channel) one Rear USB3.0 port is necessary for this project one Front-panel USB2.0 port is optional for 2U chassis... -
Page 20: Pcie Bus
F06S/F06T 2U System Contribution 3.8 PCIe BUS PCI Express* Gen1, Gen2 and Gen 3 are dual-simplex point-to point serial differential low-voltage interconnects. The signaling bit rate is 2.5 Gbit/s one direction per lane for Gen1 (8b/10b encoding), 5.0 Gb/s one direction per lane for Gen2 (8b/10b encoding) and 8.0 Gb/s one direction per lane for Gen3 (128b/130b encoding). -
Page 21: Pcie Interface
F06S/F06T 2U System Contribution PCIe Interface There are two types of Riser boards and Mezzanine board for the system. The follow table lists the details. Description F06S 2U4N System PCIe x24 Riser (1U) (1) PCIe Gen3 x16 Add-on Card support (per node) OCP Mezzanine (1) PCIe Gen3 x8 Mezzanine v1 connector (NCSI interface support) -
Page 22: Pcie Connector Pin Definition
F06S/F06T 2U System Contribution 3.9.1 PCIe Connector PIN Definition 3.9.1.1 PCIex24 Riser Slot PIN Definition Side B Golden Finger Side A Golden Finger Name Name +12v PRSNT#1 +12v +12v +12v +12v SMCLK REFCLK3+ SMDAT REFCLK3- +3.3v LAN_SMB_DAT LAN_SMB_CLK +3.3v 3.3Vaux +3.3v WAKE# PERST#... - Page 23 F06S/F06T 2U System Contribution RSVD PERn(3) PRSNT#2-2 REFCLK2+ PETp(4) REFCLK2- PETn(4) PERp(4) PERn(4) PETp(5) PETn(5) PERp(5) PERn(5) PETp(6) PETn(6) PERp(6) PERn(6) PETp(7) PETn(7) PERp(7) PRSNT#2-3 PERn(7) PETp(8) SLT_CFG0 PETn(8) PERp(8) PERn(8) PETp(9) PETn(9) PERp(9) PERn(9) PETp(10) PETn(10) PERp(10) PERn(10) PETp(11) PETn(11) PERp(11) PERn(11)
- Page 24 F06S/F06T 2U System Contribution PETp(12) PETn(12) PERp(12) PERn(12) PETp(13) PETn(13) PERp(13) PERn(13) PETp(14) PETn(14) PERp(14) PERn(14) PETp(15) PETn(15) PERp(15) PRSNT#2-4 PERn(15) PETp(16) SLT_CFG1 PETn(16) PERp(16) PERn(16) PETp(17) PETn(17) PERp(17) PERn(17) PETp(18) PETn(18) PERp(18) PERn(18) PETp(19) PETn(19) PERp(19) PERn(19) PETp(20) PETn(20) PERp(20)
- Page 25 F06S/F06T 2U System Contribution PERn(20) PETp(21) PETn(21) PERp(21) PERn(21) PETp(22) PETn(22) PERp(22) PERn(22) PETp(23) PETn(23) PERp(23) PRSNT#2-5 PERn(23) PRSNT#2-6 Table 3-2 PIN definition of PCIe x24 Riser slot 3.9.1.2 OCP Mezzanine v1 Connector PIN Definition Pin description Pin description Name Name P12V_PSU 1 MEZZ_PRSNT_N...
- Page 26 F06S/F06T 2U System Contribution SMB_MEZZ_NIC1_ CLK 15 CLK_50M_LAN_RMII SMB_MEZZ_NIC1__DAT 16 RMII_IBMC_NIC_TX_EN_S MEZZ_WAKE_N 17 RST_PERST0_N RMII_IBMC_NIC_RX_ER_S 18 SMB_MEZZ_NIC2_CLK 19 SMB_MEZZ_NIC2_DAT RMII_IBMC_NIC_TXD0_S 20 GND RMII_IBMC_NIC_TXD1_S 21 GND 22 RMII_MEZZ_NIC_RXD0 23 RMII_MEZZ_NIC_RXD1 CLK_100M_PE3_DP 24 GND CLK_100M_PE3_DN 25 GND 26 CLK_100M_10G_MEZZA_DP 27 CLK_100M_10G_MEZZA_DN P3E_CPU0_PCIE3_TX_C_DP8 28 GND P3E_CPU0_PCIE3_TX_C_DN8 29 GND...
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Page 27: Lan On Motherboard (Lom)
F06S/F06T 2U System Contribution 107 GND 47 P3E_CPU0_PCIE3_RX_DN12 108 P3E_CPU0_PCIE3_TX_C_DP13 48 GND 109 P3E_CPU0_PCIE3_TX_C_DN13 49 GND 110 GND 50 P3E_CPU0_PCIE3_RX_DP13 111 GND 51 P3E_CPU0_PCIE3_RX_DN13 112 P3E_CPU0_PCIE3_TX_C_DP14 52 GND 113 P3E_CPU0_PCIE3_TX_C_DN14 53 GND 114 GND 54 P3E_CPU0_PCIE3_RX_DP14 115 GND 55 P3E_CPU0_PCIE3_RX_DN14 116 P3E_CPU0_PCIE3_TX_C_DP15 56 GND 117 P3E_CPU0_PCIE3_TX_C_DN15... -
Page 28: Lpc Bus
F06S/F06T 2U System Contribution 3.12 LPC BUS The PCH implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. The PCH LPC bus is used to connect to the BMC and to an optional TPM device. 3.13 TPM The PCH supports TPM specification 1.2 level2 revisions 103. - Page 29 CPLD update header Pin1~8 CPLD JTAG update header HSC OCP header JP15 1-2: 33A / 420W 2-3: 46A / 587W (Default) MB Mate header Close Close: For F06 MB Open: For F06C MB Table 3-4 BIOS/BMC Jumpers Setting Figure 3-5 Jumper Location...
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Page 30: Debug Header Information
F06S/F06T 2U System Contribution 3.17 Debug header Information 3.17.1 XDP Support Standard XDP header mounted on F06 OCP motherboard for Intel Xeon E5 v3 processors (XDP) will be depopulated after production. 3.17.2 SMB Debug Header (JP7) SMB Debug Header is a SMB debug header which is connected to PCH’s HOST channel and BMC SMB channel 4. Figure 3-6 F06 OCP motherboard SMB debug Header 3.17.3 BMC Debug Header (J1 and J10) F06 OCP motherboard provides an interface to monitor BMC and host console by debug board, you need to plug... -
Page 31: Product Sensors
F06S/F06T 2U System Contribution 3.18 Product Sensors Sensor Description TMP75 Inlet temperature sensor under F06S / F06T System (U65,Q25) TMP75 Outlet temperature sensor under F06S / F06T System (U1,Q2) AST1250 Monitor CPU / System voltage and temperature (BMC) Table 3-5 F06S OCP motherboard sensor list Figure 3-9 Sensors location (air flow direction) -
Page 32: Smbus
F06S/F06T 2U System Contribution 3.19 SMBus The products must comply with the Intel Xeon E5 v3 platform SMBus architecture. This is a requirement in order to minimize BIOS / Firmware code development efforts and improve product board stability and debugging. Figure 3-10 F06 OCP motherboard BMC SMBus Block Diagram... -
Page 33: Power Consumption
F06S/F06T 2U System Contribution 3.20 Power Consumption These are max values (where available) for board VR design purposes and system. TDP power estimate for the main components are provided in below table. Table 3-6 F06S 2U4N System power consumption Table 3-7 F06T 2U2N System power consumption 3.20.1 Power Supply PINOUT F06 motherboard Power Connector (J38) Name... -
Page 34: Led Definition
F06S/F06T 2U System Contribution 3.21 LED Definition 3.21.1 HDD Active LED Location D3 LED COLOR Description Silk Screen Label Status No access Hard drive activity. This LED shall illuminate when there is activity on Blink Green the motherboards SATA hard drive interfaces, or on-board mSATA and NGFF connector interface. -
Page 35: Debug Port Switch And Led
F06S/F06T 2U System Contribution 3.21.4 Debug Port Switch and LED UART Debug port switch selection mode. 3.21.5 BMC Heart beat LED Location D10 LED COLOR Description Silk Screen Label Status Green BMC not ready HEARTBEAT LED Blink Green BMC Active... -
Page 36: Product System Requirements
F06S/F06T 2U System Contribution 4 PRODUCT SYSTEM REQUIREMENTS F06S is at 2U height with 4x hot-plug Sleds and F06T is with 2x hot-plug Sleds. The Chassis will be enabled to complement the board offering and accommodate the marketing requirements of sled with 4 F06S sleds, peripheral boards, HDDs, FANs &... -
Page 37: F06T 2U2N System View
F06S/F06T 2U System Contribution Figure 4-3 F06S 2U4N system Rear View F06T 2U2N System View Figure 4-4 F06T 2U2N System Front View... -
Page 38: System Bios And Bmc Firmware
The system BIOS and BMC FW are third party proprietary and will come with binary format along with F06S / F06T system. System BMC firmware is optional to use open BMC from Facebook or AMI based code upon the feedback from OCP community. -
Page 39: Fan
F06S/F06T 2U System Contribution Table 4-1 LED behavior of PSU 4.6 Fan Four dual-rotor & Hot swap 80mmx 56mm variable-speed Fans to meet the requirement of air-flow 125cfm for F06S system configurations. Fan signals are made available via a consolidated header on Fan board and The Fan control and Fan speed monitor are by chassis management controller: H8 on PDB. -
Page 40: Regulatory Compliance Specifications
F06S/F06T 2U System Contribution 4.8 Regulatory Compliance Specifications Planned safety and Electromagnetic Compatibility (EMC) certification are listed below but may be changed upon the feedback from OCP community. UL 60950-1, 2nd Edition CSA C22.2 No. 60950-1-07, 2nd Edition CB Scheme CB Certificate and Report to IEC 60950-1:2005, Second Edition and/or EN 60950-1: 2006 Taiwan...
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