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TH-55DX650R
9 Block Diagram
S15
S15.7
15.7
REG
REG
RE
S15.
S15.7
15.7
LNB1
LNB
NB1
LNB1
LNB
NB1
S3.3/
S3.3/S1.8
.3/S1. 1.8
Asia
As Asia
IEC
IEC
Single
Sing ngle
TU-IIC1
TU-IIC1
EXT_IFAGC1
EXT_IFAGC1
IF1
IF1
IFAGC1
IFAGC1
( Only
( Only
Taiwan
Taiwan
F
F
Centra Ame
Centra America
merica ca
Brazil )
Brazil )
Analog AV
Analog AV
R
R
L
L
OPT
OPT
S1.8
S1.8
S S 3.3
S3.3
Lch:10
Lch:10W
:10W
I2S AMP
I2S
I2S AMP
YDA176-QZ
YDA176
176-QZ
(YAMAHA)
(YAMAHA)
Rch:10
Rch:10W
:10W
< ODU
<
ODU_ON
ODU_ON
ON
>
> ODU
ODU_DET
ODU_DE
DET
Only
Only for Central Americ rica (W)
Only for Central America (W) model
(W) model
BE-IIC
BE-IIC
S3.3/
S3.3/ S1.2
.3/ S1.2
DiSE
DiSEqC1
DiSEqC1
EXT_IFAGC1
EXT_IFAGC1
<
< FE_XRST
FE_XRST
IF1
IF1
BE-IIC
BE-II IIC
(DV
(DVB-T2
DVB-T2 /T)
/T)
TU-IIC1
TU-IIC1
TU_Serial
TU_Serial_TS1
ial_TS1
SAT_AGC1
SAT_AGC1
DEMOD
DEMOD
I_1
I_1
(TU_Para_TS1)
(TU_Para_
a_TS1)
2
2
Q_1
Q_1
DiSEqC1
DiSEqC1
DiSE
41MHz
41MHz
41
All All Models
All Models
Models
S3.3/
S3.3/ S1.2
.3/ S1.2
< FE_XRST
<
FE_XRST
EXT_IFAGC1
EXT_IFAGC1
TU_Serial_TS1 / TU_Serial_TS1_J
TU_Serial_TS1 / TU_Serial_TS1_JP
IF1
IF1
BE-IIC
BE-IIC
(TU_Para_TS1)
(TU_Para_
a_TS1)
DVB-T2/T
DV
DVB-T2/T
DTM
DTMB
DTMB
TU-IIC1
TU-IIC1
ISDB-T
ISDB-T
SAT_AGC1
SAT_AGC1
TU_Serial_TS1
TU_Serial
ial_TS1
I_1
I_1
(TU_Para_TS1)
(TU_Para_
a_TS1)
(D (DEMOD
(DEMOD
Q_1
Q_1
1 )
1 )
FEAINP
FEAINP
Lo
Low-IF
Low-IF
DiSEqC1
DiSEqC1
DiSE
FEAINN
FEAINN
ADC
ADC
IF1
IF1
IFAGC1
IFAGC1
41
41MHz
41MHz
DMD
DMD
CVBS
CVB
CVBS
V-SW
V-SW
Y
Y
YPbPr
YP
YPbPr
Pb
Pb
Pr
Pr
VDAC
VDAC
L/R in x 2
L/R in x 2
A-SW
A-SW
(Thru)
(Thru)
Optical OU
Optical OUT
tical OUT
ARC
ARC OUT
RC OUT
Rx0
Rx0
HDMI1.
HDMI1.
HD
4
4
Rx1
Rx1
HDMI
HDMI
HD
HDMI1.
HDMI1.
Rx
Rx
HD
HDMI3
HDMI3
DDC* > STM
DDC
DDC* > STM
4
4
MUX
MUX
MU
HPD* < STM
HPD
HPD* < STM
x4
x4
HDMI_5V_DET* > STM
HD
HDMI_5
_5V_DET* > STM
Rx2
Rx2
HD
HDMI2.
HDMI2.
HDMI2
HD
HDMI2
DDC
DDC* > STM
DDC* > STM
0
0
HPD* < STM
HPD* < STM
HPD
HDMI_5
HDMI_5V_DET* > STM
HD
_5V_DET* > STM
Rx3
Rx3
HDMI2.
HDMI2.
HD
HD
HDMI1
HDMI1
DDC
DDC* > STM
DDC* > STM
0
0
A-Chip
A-Chip
HPD
HPD* < STM
HPD* < STM
HDMI_5V_DET* > STM
HDMI_5
HD
_5V_DET* > STM
SOUND_VCC
SOUND
UND_VCC
I2S(MCLK/LRCLK/BCLK/SDAT[1:0])
I2S(MCLK/LRC
RCLK/BC
BCLK/S /SDAT[1:0])
XRS
XRST/#SOS/#AMP_MUTE
XRST/#SOS/#AMP_MUTE
NON USED
NON USED
S5
S5
CI_POWER_ON
CI_POWER
OWER_ON >
>
<
< CI_OCP
CI_OCP
CI
CI
Power
Power
Circuit
Ci Circuit
Transport
Transpo
port
Stream
Stream
CI
CI CI
DATAIN[7:0
DATAIN[7:0]
[7:0]
CLKIN
CLKIN
SYNCIN
SYNCIN
SYNC
VAL_IN
VAL_IN
IRQ
IRQ
EA[14:0]
EA[14:0
[14:0]
DATAIN[7:0]
DATAIN[7:0
[7:0]
DATAOUT[7:0]
DATAOUT[7:0]
RESET
RESET
WAIT
WAIT
CLKIN
CLKIN
CLKOUT
CLKOU
KOUT
CE1/WE
CE1/WE
CE
CD
CD1
CD1
SYNCIN
SYNC
SYNCIN
SYNCOUT
SYNC
NCOUT
CD
CD2
CD2
OE/IOWR
OE/IOWR
1_JP
Wired OR
Wired OR
VAL_IN
VAL_IN
VALOUT
VALOUT
IORD
IORD
Internal CI
Internal CI CI
SPI-IF
SP SPI-IF
controller
controll ller
SAW
SA
SAW
FLT
FLT
DVB-C
DVB-C
Decoder
Decod
oder
SU
SUB
SUB
DVB-T
DVB-T
AV
AV
Decoder
Decod
oder
Trans Port Demux
Trans Port Demu
mux
Decod
Decoder
oder
MAIN
MAIN
ATSC/QAM
ATSC/QAM
Decoder
Decod
oder
Dec Audio
Dec Audio
B2R
B2R
2R
ATV
ATV
Digital SIF
Digital SI SIF
Decoder
Decod
oder
Digital CVBS
Digit ital CVB
CVBS
ADC
ADC
TV Decoder
TV Decoder
Pre
Pre
External Video(Analog)
Externa
ternal Vide
deo(Ana
nalog)
[0]
[0]
(IPNR)
(IPNR
IPNR)
ADC
ADC
Analog Video
Analog og Video
Processo
Processor
ssor
[3:1]
[3:1]
Pr Processo
Processor
ssor
External Video(HDMI)
Externa
ernal Vide
deo(HD
HDMI)
TVE
TVE
TV
OSD
OSD
5
5
Audio
Audio
ADC
ADC
DS
DSP
DSP
DAC
DAC
EASTE
EASTER
EASTER
SPDIF
SPDIF
SW
SW
R2R
R2R
R2
II IIC
IIC
STM-IIC
STM-II IIC
Serial
Serial
ADx8
ADx8
STM-Serial0
STM-Serial0
CLK
CLK
GEN
GEN
μP
μP
STB5V
STB5V
<
< TV_SOS
TV_SOS
AMP/HP MUTE
AMP/HP MUTE
Analog
Analog
MONITOROUT MUTE
MONITOROU
ROUT MUTE
ASIC
ASI SIC
OVP
OVP
Safety
Safet
fety
SOS
SOS
Ci Circuit
Circuit
< MON_MUTE
<
MON_MUTE
<
< SP
SP_HP_MUTE
SP_HP_MUTE
PWMA
PWMA
PW
PWM_ENB
PW
PWM_ENB >
>
PWMOUT
PWMOUT
28
S3.3
S3.3
S5/ S3.3
S5/ S3.3
Debug
Debu
bug
eMM
eMMC
MMC
32Gbit
32Gb
32Gbit
Connector
Conn
onnec ecto tor
SC
SCLK
SCLK
SD
SDI
SDI
MM
MMCCLK
MMCC
CCLK
SDO
SDO
MMCCMD
MMCC
MM
CCMD
CE
CE#1
CE#1
XERS
XERST
RST
MMCD
MM
MMCDAT0-7
CDAT0-7
S1.05
S1.05
S1.0
S1.0
S3.3
S3.3
S1.5
S1.5
SPI-IF
SP SPI-IF
DDR1.5
DDR
DDR1.5
eMMC-IF
eMM
eMMC-IF
x80
x80
OSD
OSD
DD
DDR3
DDR3
DDR3
DDR3
1,2,3
1,2,
1,2,3
x16
x16
Controller
Controller
Dec video
Dec video
curso sor
cursor
4Gbit
4Gbit
DDR3
DDR3 1866 4Gbx5
DDR3 1866
1866 4Gb
4Gbx5
T-CON
T-CO
CON
Mai
Mai
n
n
MJC
MJC
VbyOne 8 Lane (Video w OSD)
VbyOne 8 8 Lane (Video w OSD)
MIB
MIB
Scaler
Sca caler
PQ
PQ
(FR
(FRC,
(FRC,
Sub
Sub
3D)
3D
3D)
LVDS-Tx/
LVDS-Tx/
mini-LVDS-Tx
mini-LVDS-Tx
V-by-One
V-by-One
BL_ON, DISPEN, BL_SOS,PWM
BL_
L_ON, , DISPEN
SPEN, BL_SOS,PWM
TV_SUB_ON
TV_SUB_ON
TV_SUB_ON
TV_SUB_ON
KEYSCAN/POWER-KEY
KEYSCAN/POWER-KEY
KEYSCAN
KEYSCAN/POWER-KEY
KEYSCAN/POWER-KEY
KEYSCAN
D-C
D-Chip
D-Chip
USB2.0
USB2.0
USB
(Port 0)
(Port 0)
IIC
IIC
Serial
Serial
BE_IIC0
BE_II IIC0
BE
Serial
Serial
USB2.0
USB2.0
USB
BE
BE_IIC1
BE_II IIC1
1
1
USB
US
USB
(port1)
(port1)
(po
BE_IIC2
BE
BE_IIC2
IF
IF
x4
x4
AR
ARM
ARM
USB3.0
USB
USB3.0
(Port 2)
(Port 2)
Comm
Common-Reset
mmon-Rese
eset
USB
USB2.0
USB2.0
(Port3 t3)
(Port3)
SD-IF
SD-IF
ETHER-IF
ETHER-IF
ETHE
24
24MHz
24MHz
F15
F15V
15V
Paragon
Parago
gon
Rese
Reset
eset
Ci Circuit
Circuit
STB3.3
STB3.3
S3.3/1.8
S3.3/1.
.3/1.8
SDVOLC
SDVOLC
SDV
NT71933(TB
NT71933(TBD)
(TBD)
(FR
(FRC-TCON)
(FRC-TCON)
Panel
Panel
PNL TEST ON
PNL TEST ON
PCID_EN
PCID_EN
PC
?
?
LD LD
LD
LD
LD LD
P
P
P
P
S5
S5
USB*VBUS >
USB*VBU
BUS >
USB
USB
< OVCUR*
< OVCUR
OVCUR*
Power SW
Power SW
USB-1
USB-1
S5
S5
USB*VBUS >
USB*VBUS >
HDD-USB
HDD-USB
HDD
< OVCUR*
< OVCUR
OVCUR*
Power SW
Power SW
USB-2
USB-2
(HDD)
(HDD
(HDD)
S5
S5
STB5.3
STB5.3
For Wake
For Wake up On Wireless (Euro)
ake up On Wireless
ess (Euro)
USB
US
USB
Power SW
Power SW
IEEE802.11n
IEEE802
IEEE802.11n
Wireles ess UNIT
Wireless UNIT
WOW_ON_IRQ <
WOW_ON_IRQ <
< PHY
< PHY_PWR_ON
PHY_PWR
PWR_ON
> WOW_OVP
> WOW_OVP
ETHE
ETHER
HER
10/100M
10/100M
10/10
STB3.3
STB3.3
For uP
For uP
EEP
EEP
< EEPR
<
EEPROM_WP
EEPROM_WP
16
16k
16k
STB-II IIC
STB-IIC
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