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LG 50PX950 Service Manual page 31

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+5V
C429
C431
47uF
22uF
16V
10V
C434
0.1uF
R442
5V TO 2.5V
+5V
IC4005
BLM18SG700TN1D
AZ1085S-ADJTR/E1
L4010
INPUT
3
2
1
C4044
ADJ/GND
C4040
0.1uF
22uF
50V
16V
R2
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics Inc. All rights reserved.
Only for training and service purposes
5V TO 3.3V
IC402
MP8706EN-C247-LF-Z
IN
GND
1
8
SW_1
VCC
2
7
3A
C445
R451
R431
16V
SW_2
FB
22uF
0
13K
0.1uF
3
6
10V
C452
1/8W
R2
47
BST
EN/SYNC
1%
4
5
R1
L408
3.6uH
2V5
OUTPUT
C4054
C4049
0.1uF
22uF
50V
R4036
1K
1%
R1
V0 = 1.25(1+R2/R1)
+5V
3V3
C4060
47uF
C454
16V
100uF
16V
1V8
3.3V TO 1.8V
3V3
IC4006
AZ1085S-ADJTR/E1
L4011
MLB-201209-0120P-N2
INPUT
OUTPUT
3
2
C4041
C4045
1
C4050
C4055
22uF
0.1uF
22uF
0.1uF
ADJ/GND
25V
16V
16V
16V
62
82
R4037
R4035
3V3
FPGA_RESET
IC4007
FPGA_RESET
KIA7029AF
SW4001
JTP-1127WEM
R4030
330
1
2
I
O
1
3
/3D_FPGA_RESET
2
FPGA_RESET
FPGA_RESET
FPGA_RESET
3
4
C4047
G
C4051
0.1uF
0.1uF
16V
16V
5V TO 1.2V
IC4008
MP8706EN-C247-LF-Z
IN
GND
1
8
SW_1
VCC
C4061
2
7
22uF
3A
10V
R452
R4047
SW_2
FB
47K
10K
3
6
C4062
1/10W
R2
0.1uF
1%
47
BST
EN/SYNC
4
5
R4045
R1
L4012
3.6uH
Vout=0.8*(1+R1/R2)
DDR VTT
DDR_VTT
C4035
C4038
C4032
100uF
10uF
0.1uF
16V
16V
16V
DDR_VREF0
L4008
BLM18PG121SN1D
READY
C4039
C4043
C4034
C4037
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
DDR_VREF1
L4009
BLM18PG121SN1D
C4033
C4036
0.1uF
0.1uF
16V
16V
1V2
C4066
C4064
16V
22uF
100uF
0.1uF
10V
C4065
16V
3V3
IC4004
BD35331F-E2
1V8
GND
VTT
1
8
EN
VTT_IN
2
7
VTTS
VCC
3
6
R4038
VREF
VDDQ
220
4
5
C4052
C4056
C4057
2.2uF
0.1uF
10uF
25V
10V
16V
3DTV
2010. 02. 11
3DF_POWER
3
3
LGE Internal Use Only

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