Pin No.
Pin Name
46
FOK
47
VP
48
MON3
49
MON2
50
MON1
51
MON0
52
DEFECT
53
PPIT
54
READ
55
PLG-I
56
RESET
57
HOLDER
58
FSEQ
59
SHOCK
60
WRQB
61
CHG-O
62
NIHM-O
63
BSTSW
64
BST2
65
BST3
66
HP/LINE
67
LED1
68
VSS3
69
VDD3
70
CHG-1
71, 72
NC
73
P-CONT
74
AMUTE
75
RMCDT
76
PWSTB
77
DNSW
78
DRAMSW
79
JAPAN
80
TEST
I/O
I
FOK signal input.
I
VP (CLV servo lock check) signal input.
I
Monitor 3 signal input from LC896431.
I
Monitor 2 signal input from LC896431.
I
Monitor 1 signal input from LC896431.
I
Monitor 0 signal input from LC896431.
I
DEFECT signal input.
I
PPIT signal input.
O
Output H when reading data.
I
Insertion detection signal input of head phone jack (L: inserted).
O
LC896431 reset signal output.
I
Holder OPEN (H)/CLOSE (L) signal input & standby release.
I
FSEQ signal input of LC896431.
I
SHOCK detection of LC896431.
I
Signal input from LC896431.
O
Battery charge stand control output.
O
Battery charge output.
O
Head phone amplifier bus boost ON/OFF switch (BST on with H).
O
DSL 3 STEP switch output.
O
DSL 3 STEP switch output.
O
Head phone amplifier/line switch output.
O
Operation LED control signal output (LED on with H).
Connected to GND.
Connected to VDD.
O
Battery charge stand LED control output.
Not connected.
O
System power supply control (L: turn on the power supply).
O
AUDIO MUTE signal output (H: turn on MUTE).
O
Serial data output to liquid crystal remote controller.
O
Standby signal output of headphone driver (L: standby).
O
L when BATT is above 1.8V. H when CHGINT = L.
O
Power supply control output of DRAM (L: turn on the power supply of DRAM).
I
Domestic/Overseas version switch input (H: domestic).
I
Test mode/Main mode switch input (L: test mode).
18
Description