abaco systems PCI-5565PIORC Hardware Reference Manual
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abaco systems PCI-5565PIORC Hardware Reference Manual

Ultrahigh speed fiberoptic reflective memory with interrupts
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Hardware Reference Manual
PCI-5565PIORC* Ultrahigh Speed Fiber-
Optic Reflective Memory with Interrupts
THE PCI-5565PIORC IS DESIGNED TO MEE T THE EUROPEAN UNION (EU)
RESTRICTIONS OF HAZARDOUS SUBSTANCE (RoHS) DIRECTIVE (2002/95/EC)
CURRENT REVISION.
Publication No. 500-9367855565-000 Rev. D.0

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Summary of Contents for abaco systems PCI-5565PIORC

  • Page 1 Hardware Reference Manual PCI-5565PIORC* Ultrahigh Speed Fiber- Optic Reflective Memory with Interrupts THE PCI-5565PIORC IS DESIGNED TO MEE T THE EUROPEAN UNION (EU) RESTRICTIONS OF HAZARDOUS SUBSTANCE (RoHS) DIRECTIVE (2002/95/EC) CURRENT REVISION. Publication No. 500-9367855565-000 Rev. D.0...
  • Page 2 WEEE is processed in accordance with the requirements of the WEEE Directive. Abaco Systems will evaluate requests to take back products purchased by our customers before August 13, 2005 on a case-by-case basis. A WEEE management fee may apply.
  • Page 3 About This Manual Conventions Notices This manual may use the following types of notice: WARNING Warnings alert you to the risk of severe personal injury. CAUTION Cautions alert you to system danger or loss of data. NOTE Notes call attention to important features or instructions. Tips give guidance on procedures that may be tackled in a number of ways.
  • Page 4 Further Information Abaco Website You can find information regarding Abaco Systems products on the following website: LINK www.abaco.com Abaco Documents This document is distributed via the Abaco website. You may register for access to manuals via the website. LINK www.abaco.com/products/pci-5565piorc...
  • Page 5 Do not return products without first contacting the Abaco Repairs facility. Additional Notes The PCI-5565PIORC* is the PCI-based member of Abaco’s family of Reflective Memory real-time fiber-optic network products. Two or more PCI-5565PIORCs, along with other members of this family, can be integrated into a network using standard fiber-optic cables.
  • Page 6 The PCI-5565PIORC adds greater design flexibility and improved performance over the classic PCI-5565 in at least three areas. 1. The PCI-5565PIORC’s DMA burst and PIO single read access rates have an improvement over the classic PCI-5565. 2. The PCI-5565PIORC’s access bandwidth for the onboard SDRAM memory has doubled, improving the overall throughput.
  • Page 7 Because the two registers groups physically reside in separate devices, they are accessed through different regions of memory. The PCI-5565PIORC, on the other hand, contains both groups of registers within the same FPGA. The two groups could have been combined. However to provide software continuity and backward compatibility, the two register groups have been maintained separately as in the classic VMIPCI-5565.

  • Page 8: Figure 1 Block Diagram Of Pci-5565Piorc

    Optics 2.125 GHz SERDES 16-bit 106.25 MHz FIFO FIFO 32-bit Data Memory Main FPGA 4-bit Parity 133 MHz PCI Core 32/64-bit at 33/66 MHz PCI bus 8 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 9: Figure 2 Typical Reflective Memory Network

    Figure 2Typical Reflective Memory Network VMIVME-5565 PCI-5565PIORC NODE 0 PCI WorkStation with NODE 1 PCI-5565PIORC VMEbus Chassis with VMIVME-5565 PMC-5565PIORC VMEbus Chassis with NODE 255 PMC-5565PIORC Up to 300m between nodes for multimode Up to 10km between nodes for single mode Publication No.
  • Page 10 Because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modification to the product. Return the product to Abaco for service and repair to ensure that safety features are maintained. 10 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...
  • Page 11 Compliance Information This chapter provides the applicable information regarding regulatory compliance for the PCI-5565PIORC. Abaco has evaluated the PCI-5565PIORC has met the requirements for compliance to the following standards: • BS EN55024 • BS EN55022, Class A • IEC61000-4-2 • IEC61000-4-3 International Compliance It has also met the following international levels.
  • Page 12 Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. Canadian Regulations The PCI-5565PIORC Class A digital apparatus complies with Canadian ICES-003. NOTE Any equipment tested and found compliant with FCC Part 15 for unintentional radiators or EN55022 (previously CISPR 22) satisfy ICES-003.

  • Page 13: Table Of Contents

    Table of Contents 1 • Handling and Installation ........... . . 17 1.1 Unpacking Procedures.
  • Page 14 Figure 1-5 Example: Six Node Ring Connectivity PCI-5565PIORC ....... . .
  • Page 15 List of Tables Table 1-1 Example Node ID Switch S2 RFM-5565 ........... . . 19 Table 1-2 Switch S1 Configuration RFM-5565 .
  • Page 16 Table 3-52 PCI PIO Window Selections ............. 63 16 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts...

  • Page 17: Handling And Installation

    All claims arising from shipping damage should be filed with the carrier and a complete report sent to Abaco Systems Customer Care. 1.2 Handling Precaution Some of the components assembled on Abaco’s products may be sensitive to electrostatic discharge and damage may occur on boards that are subjected to a high-energy electrostatic field.

  • Page 18: Switch S1 And S2 Configuration

    (OFF position). S1 position 7 is currently reserved and should not be used (left in the OFF position). 18 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 19: Table 1-1 Example Node Id Switch S2 Rfm-5565

    NOTE S1 position 8 should be set in the ON position only when a flash update of the control logic has failed. After a successful flash update of the control logic, S1 position 8 should be set in the OFF position. Table 1-1 Example Node ID Switch S2 RFM-5565 Node ID Position...

  • Page 20: Figure 1-1 S1 And S2 Location Pci-5565Piorc

    Figure 1-1 S1 and S2 Location PCI-5565PIORC 20 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 21: Physical Installation

    Side View Isometric View NOTE The PCI-5565PIORC is designed to interface with any suitable PCI compliant motherboard using a direct PCI bus interface, compliant with V2.2 of the PCI signaling specification as defined by IEEE P1386.1 Draft 2.0. Publication No. 500-9367855565-000 Rev. D.0...

  • Page 22: Front Panel Description

    CAUTION When fiber-optic cables are not connected, the supplied dust caps need to be installed to keep dust and dirt out of the optics. Do not power up the PCI-5565PIORC without the fiber-optic cables installed. This could cause eye injuries.

  • Page 23: Led Description

    1.5.1 LED Description Table 1-4 LED Descriptions Color Description Status User defined board status indicator. Signal Detect Yellow Indicates optical network connection. Own Data Green Indicates when own data is received. The status LED’s power-up default state is ON. The status LED is a user defined board indicator and can be toggled ON or OFF by writing to Bit 31 of the Control and Status register.

  • Page 24: Figure 1-4 Lc Type Fiber-Optic Cable Connector

    (4.5mm) 0.49 (1.25) Dimensions: inches (mm) Figure 1-5 Example: Six Node Ring Connectivity PCI-5565PIORC Node 1 Node 2 Node 3 Node 6 Node 5 Node 4 24 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 25: Theory Of Operation

    2 • Theory of Operation The following sections describe the functionality of the RFM-5565 Reflective Memory board. A description of the major sub-circuits and their operation is included. This section will also occasionally mention Control and Status registers related to operations. To see a detailed description of these Control and Status registers please refer to Chapter 3, ʺProgrammingʺ...

  • Page 26: Rfm-5565 Register Sets

    Status Registers do NOT replace the first $40 locations of RAM. The offset address range is $0 to $7FFFFFF for the 128 MBytes and $0 to $FFFFFFF for the 256-MByte option. 26 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 27: Interrupt Circuits

    2.5 Interrupt Circuits The RFM-5565 has a single interrupt output (INTA#). One or more events on the RFM-5565 board can cause the interrupt. The sources of the interrupt can be individually enabled and monitored through several registers. The interrupt circuitry of the RFM-5565 is arranged in two tiers. The primary tier of interrupts is enabled and monitored by the Local Configuration Register’s INTCSR at offset $68.

  • Page 28: Figure 2-1 Interrupt Circuitry Block Diagram

    (per Base Address Register 0 or 1) DMA 0 Done Bits 11 and 15 Bits 18 and 21 Interrupt Control and Status Register (INTCSR) (Offset $68) Primary Tier Interrupts Host Interrupt (INTA#) 28 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 29: Network Interrupts

    2.6 Network Interrupts The RFM-5565 is capable of passing interrupt packets, as well as data packets, over the network. The network interrupt packets can be directed to a specific node or broadcast globally to all nodes on the network. Each network interrupt packet contains the sender’s node ID, the destination node ID, the interrupt type and 32 bits of user defined data.

  • Page 30: Rogue Packet Removal Operation

    Rogue Master. Otherwise, one of the two will erroneously remove packets marked by the other. 30 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 31: Programming

    3 • Programming Basic target write and read operations of the RFM-5565 require little or no software. The board powers up in a functional mode. The user will need to access the PCI Configuration registers (Base Address Register 0, 1, 2 and 3) to learn where the system BIOS has located the other register sets and the Reflective Memory.

  • Page 32: Pci Configuration Registers

    PCI Configuration ID: Offset $00 Value after Description Read Write PCI Reset 15:0 Vendor ID. $114A Identifies manufacturer of device. 31:16 Device ID. $5565 Identifies particular device. 32 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 33: Table 3-3 Pci Command Register

    Table 3-3 PCI Command Register PCI Command: Offset $04 *Value after Description Read Write PCI Reset I/O Space. Writing a one (1) allows the device to respond to I/O Space accesses. Writing a zero (0) disables the device from responding to I/O Space accesses. Memory Space.

  • Page 34: Table 3-4 Pci Status Register

    PCI bus parity error, even if parity error handling is disabled (the Parity Error Response bit in the Command register is clear). Writing a one (1) clears this bit to zero (0) 34 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 35: Table 3-5 Pci Revision Id Register

    Table 3-5 PCI Revision ID Register PCI Revision ID: Offset $08 Value after Description Read Write PCI Reset Revision ID. Revision of board Yes Current Rev# Table 3-6 PCI Class Code Register PCI Class Code: Offset $09 Value after Description Read Write PCI Reset...

  • Page 36: Table 3-10 Pci Built-In Self Test Register

    PCI Base Address Register 1 contains the starting address for I/O mapped accesses to Local Configuration Registers. The value in this register is loaded by the system BIOS. 36 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 37: Table 3-12 Pci Base Address Register 1 For Access To Local Configuration Registers

    Table 3-12 PCI Base Address Register 1 for Access to Local Configuration Registers PCIBAR1: Offset $14 *Value after Description Read Write PCI Reset Memory Space Indicator. A zero (0) indicates the register maps into Memory Space. A one (1) indicates the register maps into I/O Space. (NOTE: Hardcoded to one (1).) Reserved.

  • Page 38: Table 3-14 Pci Base Address Register 3 For Access To Reflective Memory

    PLD Applications PCI-X core. These registers should be considered reserved and remain unaltered by the user. Table 3-15 PCI Base Address Register 4 PCIBAR4: Offset $20 Value after Description Read Write PCI Reset 31:0 Reserved. 38 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 39: Table 3-16 Pci Base Address Register 5

    Table 3-16 PCI Base Address Register 5 PCIBAR5: Offset $24 Value after Description Read Write PCI Reset 31:0 Reserved. Table 3-17 PCI Cardbus CIS Pointer Register PCI Cardbus CIS Pointer: Offset $28 Value after Description Read Write PCI Reset 31:0 Cardbus Information Structure Pointer for PCMCIA.

  • Page 40: Table 3-21 Pci Capability Pointer Register

    PCI bus. Value is a multiple of ¼ μsec increments. NOTE The RFM-5565 does not support the optional Power Management, Hot Swap and Vital features of the 40 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 41: Local Configuration Registers

    PCI Specification. 3.2 Local Configuration Registers The Local Configuration Registers are memory cycle accessible at the offsets from the value stored in Base Address Register 0. The registers at offsets $00 to $FF are also I/O cycle accessible at the offsets from the value stored in Base Address Register 1.

  • Page 42: Table 3-27 Mode/Dma Arbitration Register

    Writing a one (1) specifies use of Big Endian data ordering for DMA Channel 0 accesses to the RFM Address Space. Writing a zero (0) specifies Little Endian ordering. 42 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 43: Table 3-29 Interrupt Control And Status Register

    Table 3-29 Interrupt Control and Status Register INTCSR: BAR0/1 Offset $68 Value after Description Read Write PCI Reset Reserved PCI Interrupt Enable. Writing a one (1) enables PCI interrupts. 10:9 Reserved Local Interrupt Input Enable. Writing a one (1) enables a local interrupt (i.e., RFM interrupts) to assert a host Interrupt.

  • Page 44: Table 3-31 Intcsr Interrupt Status

    DMAPADR0: BAR0/1 Offset $84 Value after Bits Description Read Write PCI Reset 31:0 PCI Address Register. Indicates from where in PCI Memory space DMA transfers (read or write) start. 44 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 45: Table 3-35 Dma Channel 0 Local Address Register

    Table 3-35 DMA Channel 0 Local Address Register DMALADR0: BAR0/1 Offset $88 Value after Bits Description Read Write PCI Reset 31:0 Local Address Register. Indicates from where in Local Memory space DMA transfers (read or write) start. Table 3-36 DMA Channel 0 Transfer Size (Bytes) Register DMASIZ0: BAR0/1 Offset $8C Value after Description...

  • Page 46: Table 3-39 Dma Channel 0 Pci Dual Address Cycles Upper Address

    Local Address Space 1 Enable. A one (1) enables decoding of PCI addresses for PIO addresses for PIO Direct Slave access to Local Address Space 1 (PCIBAR3). Reserved 46 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...
  • Page 47 Table 3-41 PCI PIO Direct Slave Local Base Address (Remap) (Continued) LAS1BA: BAR0/1 Offset $F4 Value after Description Read Write PCI Reset 31:4 Remap PCIBAR3 Base Address to Local Address Space 1 Base Address. The PCIBAR3 base address translates to the Local Address Space 1 Base Address programmed in this register.

  • Page 48: Rfm Control And Status Registers

    127 loc. By 32-bit FIFO for network Int. 4 SID4 Int. 4 Sender ID read/clear 127 loc. Deep FIFO/ write clears pointers $3F..3D Reserved 48 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 49: Board Revision Register

    3.3.1 Board Revision Register Board Revision (BRV) BAR2 (Offset $0): An 8-bit register used to represent revisions or model numbers. This register is read-only. 3.3.2 Board ID Register Board ID (BID) BAR2 (Offset $1): An 8-bit register which contains an 8-bit code unique to the RFM-5565 type boards.
  • Page 50 4 (‘1’ when ON, ‘0’ when OFF). These two bits indicate the memory PCI PIO window size as defined in the following table. The two bits are read only. 50 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 51: Table 3-44 Pci Pio Window Sizes

    Table 3-44 PCI PIO Window Sizes Window 1 Window 0 PCI PIO Window Size default = installed memory size 64 MBytes 16 MBytes 2 MBytes Bits 21 and 20: Config 1 and Config 0 – These two bits indicate the installed memory size as defined in the following table.

  • Page 52: Table 3-46 Offset 1 And Offset 0

    (not latched) and is read-only. Bit 01: Bad Data – A logic high (1) indicates the board receiver circuit has detected bad (invalid) data at least once since 52 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 53: Local Interrupt Control Registers

    powerup or since the flag had previously been cleared. Under normal operating conditions, this event should not occur and may indicate a loss of data. This bit is read-only within this register. To clear this condition, write to the corresponding bit within the Local Interrupt Status Register. Bit 00: Own Data –...
  • Page 54 Once set, it must be cleared by writing a zero to this bit location. The assertion of the RX FIFO Almost Full bit indicates the receiver circuit is operating at maximum 54 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...
  • Page 55 capacity. If it does occur, the PCI bus master should temporarily suspend all write and read operations to the board. Bit 08: Bad Data – When this bit is high (1), the receiver circuit has detected invalid data one or more times. This bit is latched. Once set, it must be cleared by writing a zero to this bit location.

  • Page 56: Network Target Data Register

    The NIC is both read and write accessible. Only writing to the NIC register will initiate the network interrupt. The network interrupt is transmitted in order following after all previously written data. 56 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 57: Interrupt 1 Sender Data Fifo

    Table 3-49 Network Interrupt Command Register NIC: BAR2 Offset $1D NIC[3,2,1,0] Function X000 Reset Node Request (sets LISR Bit 03 only, the user application must perform the actual reset X001 Network Interrupt 1 (stored in a 127 deep FIFO at the receiving node) X010 Network Interrupt 2 (stored in a 127 deep FIFO at the receiving node) X011...

  • Page 58: Interrupt 2 Sender Id Fifo

    3.3.17 Interrupt 4 Sender ID FIFO Interrupt 4 Sender ID FIFO (SID4) BAR2 (Offset $3C): An 8-bit FIFO functioning just like SID1, except it responds only to type 4 network interrupts. 58 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 59: Figure 3-1 Block Diagram Of The Network Interrupt Reception Circuitry

    Figure 3-1 Block Diagram of the Network Interrupt Reception Circuitry Network Transmitter Receiver Network Input Circuitry Circuitry Output Interrupt Detection and Routing Circuitry Network Network Network Network Network Network Network Network Interrupt 1 Interrupt 1 Interrupt 2 Interrupt 2 Interrupt 3 Interrupt 3 Interrupt 4 Interrupt 4...

  • Page 60: Example Of A Block Dma Operation For Rfm-5565

    DMACSR0 as follows. This is necessary when using DMA interrupts. DMA channel 0 Command/Status register: DMACSR0 at PCIBAR0 + offset $A8. Write $8 to clear the DMA completion bit before attempting another DMA. 60 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 61: Example Of A Scatter-Gather Dma Operation For Rfm-5565

    3.5 Example of a Scatter-Gather DMA Operation for RFM-5565 Scatter-Gather DMA transfer is a mode usually used to perform large data transfers separated into multiple smaller pages or blocks. Note that a data page must not cross a 4-GByte address boundary. The DMA descriptor pointer is the address for a chained list of page descriptors.

  • Page 62: Table 3-51 Dma Channel 0 Mode Settings

    DMACSR0 as follows. This is necessary when using DMA interrupts. DMA channel 0 Command/Status register: DMACSR0 at PCIBAR0 + offset $A8. Write $8 to clear the DMA completion bit before attempting another DMA. 62 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 63: Example Of A Pci Pio Sliding Window Operation For Rfm-5565

    3.6 Example of a PCI PIO Sliding Window Operation for RFM-5565 RFM-5565 cards are currently available with 128 or 256 MBytes of installed memory. Under some circumstances, it is useful to reduce the PCI memory address space window size. For example, a BIOS may have difficulty dividing the address space into enough windows with appropriate granularity for all of the installed devices.
  • Page 64 DMA (Local-to-PCI and PCI-to-Local) can be used normally to transfer up to $7FFFFF bytes with another location on the PCI bus regardless of the Remap value. 64 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts Publication No. 500-9367855565-000 Rev. D.0...

  • Page 65: Example Of Network Interrupt Handling

    3.7 Example of Network Interrupt Handling The following is an example of the steps necessary to set up the RFM-5565 to generate a PCI interrupt in response to one of the four basic network interrupts. This example also lists the steps necessary to service that interrupt. When using this example, it is advisable to examine Figure 2-1 Figure 3-1...
  • Page 66 © 2016 Abaco Systems, Inc. All rights reserved. Information Centers For more information, please visit the * indicates a trademark of Abaco Systems, Inc. and/or its affiliates. All other Abaco Systems website at: Americas: trademarks are the property of their 1-866-652-2226 (866-OK-ABACO) respective owners.

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