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IC4 VHiLC32V4265B: 4M D-RAM (LC32V4265B)
Pin No.
Terminal Name
1
VCC
2-5
MDATA0-MDATA3
6
VCC
7-10
MDATA4-MDATA7
11*-14*
N.C.
15
WEB
16
RASB
17*
N.C.
18-21
ADRS0-ADRS3
22
VCC
23
VSS
24-28
ADRS4-ADRS8
29
OEB
30
UCASB
31
LCASB
32*-34*
N.C.
35-38
MDATA8-MDATA11
39
VSS
40-43
MDATA12-MDATA15
44
VSS
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Clock generator No. 1
RAS
UCAS
LCAS
Mode control
Refresh counter
Low address
buffer
A0
A8
Column
address buffer
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Power supply.
Data I/O.
Power supply.
Data I/O.
Not used.
Write enable.
Low address strobe.
Not used.
Address input.
Power supply.
Ground
Address input.
Output enable.
Column address strobe. (Lower byte control)
Column address strobe. (Upper byte control)
Not used.
Data I/O.
Ground
Data I/O.
Ground
44
43
42
41
40
39
38
37
36
35
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Clock generator No. 2
262144 memory cells
x 16 bits
512
512x16
Sense ampllfler I/O gate
512
Column decoder
Pre-decoder
Figure 47 BLOCK DIAGRAM OF IC
– 47 –
Function
34
33
32
31
30
29
28
27
26
25
Clock generator No. 3
Lower byte
Upper byte
Data input buffer
I/O1 to I/O8
I/O9 to I/O16
Data output buffer
I/O1 to I/O8
I/O9 to I/O16
Substrate bias generator
CD-MP700/CD-MP77
24
23
VCC
VSS
WE
I/O1
I/O16
OE
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