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IC1 VHiLC78646E-1: CD Servo (LC78646E)
SLCO
1
SLCIST
2
EFMIN
3
RF
4
RFVDD
5
RFVSS
6
7
FIN1
FIN2
8
9
TIN1
TIN2
10
11
VREF
12
REF1
13
FE
TEC
14
15
TE
16
RFMON
JITTC
17
ADAVDD
18
19
ADAVSS
20
TDO
SBCK/CONT6
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80
79
78
77
76
75 74
73
72 71
LC78646E
21
22
23
24
25
26 27
28
29 30
FIN1
+
–
MIX
AGC
+
–
FIN2
+
LPF
–
TIN1
+
+
TBAL
–
–
TIN2
+
TBAL
–
LEVEL SET
REF1
RAM
DETECT
SERVO PROCESSOR
A/D
ADIN
ADAVDD
ADAVSS
JITTER
JITTC
DETECT
SLCO
SLICE LEVEL
EFMIN
CONTROL
SLCIST
PCK
PDO1
PDO2
PLL
FR
PCKIST
VCEC
VVDD
CLV,CAV
VVSS
CONTROL
SBCK/FG
XIN
XOUT
CLOCK
16MOUT
XVDD
GENERATOR
XVSS
*RES
ERROR
*WRQ
CL
CORRECTION
COMMAND
CE
DI
AUDIO CD
INTERFACE
DO
VDD5V
GENERAL-PURPOSE
CONT1, 2, 3
INTERPOLATION
CONT4, 5
PORTS
MUTE
8FS
ATTENUATION
DEEMPHSIS
DIGITAL FILTER
1bit DAC
LPF
TEST
Figure 43 BLOCK DIAGRAM OF IC
70
69 68
67
66 65
64
63 62
31
32 33
34
35 36
37
38 39
RFVDD
RFVSS
EQ
PH
BH
LPF
SW
+
–
LPF
+
+
–
–
MONI
–
RFMON
+
CONT
VREF
TRACK JUMP
LDD
APC
LDS
AUTO ADJUST
FD0
SW
D/A
TD0
S/H
SLD0
SPD0
DRF
GPDAC
DRF
VDD
RUPTURE DEFECT
FRAME SYNC
DETECT,PROTECT INSERT,
FSEQ
EFN DECODE
V/*P
SUBCODE DECODE CRC
VDD
VSS
MONITOR SIGNAL SELECTOR
MONI1~5
RAM
FSK/16MIN
C2F
EFLG
AUDIO OUT
DOUT
LRCK
SERIAL
BCK
OUT
DATA
EXTERNAL
ASLRCK
ASDQCK
AUDIO IN
ASDFIN
– 43 –
CD-MP700/CD-MP77
61
60
DATA
BCK
59
58
LRCK
57
ASDFIN
56
ASDACK
55
ASLRCK
54
16MOUT
53
EFLG
52
C2F
51
XVSS
50
FSX/16MIN
49
XIN
48
XOUT
47
XVDD
46
RVDD
45
RCHO
44
RVSS
43
LVSS
42
LCHO
41
LVDD
40
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