Terasic MTLC User Manual
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Terasic MTLC User Manual

Capacitive multi-touch lcd with camera module
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Summary of Contents for Terasic MTLC

  • Page 2: Table Of Contents

    ......................1 1.1 About the Package ............................3 1.2 Setup License for Terasic Multi-Touch IP ....................4 1.3 Assembly of MTLC onto Boards with HSMC Connectors ................ 5 1.4 Connectivity ............................... 7 1.5 Getting Help ............................... 9 ARCHITECTURE OF MTLC CHAPTER 2 ..................

  • Page 3: Chapter 1 Introduction

    A HSMC cable is provided to interface with various Terasic FPGA development boards, such as Terasic DE2-115 and TR4 development boards through a HSMC interface on the MTLC. The kit contains complete reference designs and source code for camera, sensing, and painter demonstrations.
  • Page 4  Column and row binning modes to improve image quality when resizing  Simple two-wire serial interface  Programmable controls: gain, frame rate, frame size, exposure Table 1-2 shows the key parameters of the CMOS sensor (Note*). MTLC User Manual www.terasic.com May 22, 2014...

  • Page 5: About The Package

    Note: for more detailed information of the LCD touch panel and CMOS sensor module, please refer to their datasheets respectively. The kit includes everything users need to run the demonstrations and develop custom designs, as shown in Figure 1-2. MTLC User Manual www.terasic.com May 22, 2014...

  • Page 6: Setup License For Terasic Multi-Touch Ip

    Figure 1-2 MTLC kit package contents To utilize the multi-touch panel in a Quartus II project, the Terasic Multi-Touch IP is required for operation. Error messages will be displayed if the license file for the Multi-Touch IP is not added before compiling projects. The license file is located at: MTLC System CD\License\license_multi_touch.dat...

  • Page 7: Assembly Of Mtlc Onto Boards With Hsmc Connectors

    FPGA boards that are equipped with HSMC connectors on top: Figure 1-5 Fixed components in a MTLC kit Inside every MTLC kit package, there should be 2 sets of copper pillars, screws, and nuts as shown in Figure 1-5...
  • Page 8 Figure 1-7 Install copper pillars and nuts on the mounting hole The HSMC cable should be already connected to the MTLC right out of the box. User only needs to connect the HSMC cable to the HSMC connector on the host board as shown in Figure 1-8.

  • Page 9: Connectivity

    Figure 1-9. Figure 1-9 Fasten screws through the HSMC cable to the copper pillars Here we provide examples of MTLC being connected to different FPGA development boards: Arrow’s SoCKit, TR4, DE2-115, and Altera Cyclone V SoC FPGA development board (C5SoC).
  • Page 10 Figure 1-10 MTLC Connect C5S Figure 1-11 MTLC Connect TR4 Figure 1-12 MTLC Connect DE2-115 MTLC User Manual www.terasic.com May 22, 2014...

  • Page 11: Getting Help

    Figure 1-13 MTLC Connect C5SOC Here is the contact information if you encounter any problem: Terasic Technologies Tel: +886-3-575-0880 Email: support@terasic.com MTLC User Manual www.terasic.com May 22, 2014...

  • Page 12: Architecture Of Mtlc

    Chapter 2 Architecture of MTLC This chapter provides information regarding features and architecture of the Terasic Capacitive Multi-touch LCD and Camera Module. The key features of this module are listed as follows:  800x480 pixel resolution LCD with 24-bit color depth ...

  • Page 13: Block Diagram Of The Mtlc

    Figure 2-1 MTLC PCB and Component Diagram (Top) Figure 2-2 MTLC PCB and Component Diagram (Bottom) Figure 2-3 gives the block diagram of the MTLC board. The HSMC connector houses all the MTLC User Manual www.terasic.com May 22, 2014...
  • Page 14 HSMC cable. Thus, the user can configure the FPGA to implement any system design. Figure illustrates the connection for MTLC to the Terasic FPGA boards. Figure 2-3 Block Diagram of MTLC Figure 2-4 Connection Diagram of MTLC Kit with Terasic FPGA boards MTLC User Manual www.terasic.com May 22, 2014...

  • Page 15: Using Mtlc

    (800x480) to provide users the best display quality for developing applications. The LCD panel supports 24-bit parallel RGB data interface. The MTLC is also equipped with a Touch controller, which can read the coordinates of the touch points through a serial port interface.
  • Page 16 Horizontal Front Porch thfp tCLK Horizontal Valid tCLK Vertical Period Vertical Pulse tvpw Width tvpw 23th Vertical Back Porch fixed Vertical Front Porch tvfp Vertical Valid Setup time Tdsu Hold time Tdsu MTLC User Manual www.terasic.com May 22, 2014...
  • Page 17 Left or Right Display LCD_SHLR Control 2.5V Down Display LCD_UPDN Control 2.5V LCD_VSD Vertical sync input. 2.5V TOUCH _I2C_SCL touch I2C clock 2.5V TOUCH _I2C_SDA touch I2C data 2.5V TOUCH _INT_n touch interrupt 2.5V MTLC User Manual www.terasic.com May 22, 2014...

  • Page 18: Using 5 Megapixel Digital Image Sensor

    The MTLC is equipped with a 5 megapixel digital image sensor that provides an active imaging array of 2,592H x 1,944V. It features low-noise CMOS imaging technology that achieves CCD image quality. In addition, it incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode.

  • Page 19: Using The Digital Accelerometer

    The MTLC is equipped with a digital accelerometer sensor module. The ADXL345 is a small, thin, ultralow power assumption 3-axis accelerometer with high resolution measurement. Digitalized output is formatted as 16-bit twos complement and can be accessed either using SPI interface or I2C interface. This chip uses the 3.3V CMOS signaling standard. Main applications include medical instrumentation, industrial instrumentation, personal electronic aid and hard disk drive protection etc.

  • Page 20: Using Terasic Multi-Touch Ip

    Terasic Multi-Touch IP is provided for developers to retrieve user inputs, including multi-touch gestures and single-touch. The file name of this IP is i2c_touch_config and it is encrypted. To compile projects with the IP, users need to install the IP license first. For license installation, please refer to section 1.2 Setup License for Terasic Multi-Touch IP...
  • Page 21 Zoom In 0x48 Zoom Out 0x49 Note: The Terasic Multi-Touch IP can also be found under the \IP folder in the system CD as well as the \IP folder in the reference designs. MTLC User Manual www.terasic.com May 22, 2014...

  • Page 22: Chapter 4 Mtlc Demonstrations

    DE2-115 development board with MTLC. These demonstrations are particularly designed (or ported) for MTLC, with the goal of showing the potential capabilities of the kit and showcase the unique benefits of FPGA-based SOPC systems such as reducing BOM costs by integrating powerful graphics and video processing circuits within the FPGA.
  • Page 23 3.5 Using Terasic Multi-Touch IP in this document. Figure 4-1 Block Diagram of the Painter Demonstration  Demonstration Source Code  Project directory: Painter  Bit stream used: Painter.sof  Nios II Workspace: Painter \Software  Demonstration Batch File...
  • Page 24 Figure 4-4 shows the phone when counter-clockwise rotation gesture is detected. Figure 4-5 shows the photo when zoom-in gesture is detected. Figure 4-2 GUI of Painter Demo Figure 4-3 Single Touch Painting MTLC User Manual www.terasic.com May 22, 2014...
  • Page 25 Figure 4-4 Counter-clockwise Rotation Gesture Figure 4-5 Zoom-in Gesture Note: execute the test.bat under Picture_Viewer\demo_batch will automatically download the .sof and .elf file. MTLC User Manual www.terasic.com May 22, 2014...

  • Page 26: Picture Viewer

    CPU decodes the images and fills the raw result data into frame buffers in SDRAM. The VEEK-MT( DE2-115 + MTLC) will show the image the buffer being displayed points to. When users touch the LCD touch panel, it will proceed to display the next buffered image or last buffered image.
  • Page 27 Touch anywhere on the screen to resume and to return to menu. Figure 4-7 Picture Viewer Demonstration Note: execute Picture_Viewer.bat under Picture_Viewer\demo_batch will automatically download the .sof and .elf file. MTLC User Manual www.terasic.com May 22, 2014...

  • Page 28: Video And Image Processing

    These functions allow you to fully integrate common video functions with video interfaces, processors, and external memory controllers. The example design uses an Altera Cyclone® IV E EP4CE115F29 featured VEEK-MT ( DE2-115 + MTLC). A video source is input through an analog composite port on VEEK-MT which generates a digital output in ITU BT656 format.
  • Page 29 Video and Image Processing block diagram. Figure 4-8 VIP Example SOPC Block Diagram (Key Components)  Demonstration Source Code  Project directory: VIP  Bit stream used: VIP.sof  Nios II Workspace: VIP\Software MTLC User Manual www.terasic.com May 22, 2014...
  • Page 30 Figure 4-9 Note: (1).Executing VIP\demo_batch\ VIP.bat will download .sof and .elf files. (2).You may need additional Altera VIP suite Megacore license features to recompile the project. Figure 4-10 illustrates the setup for this demonstration. MTLC User Manual www.terasic.com May 22, 2014...

  • Page 31: Camera Application

    This demonstration shows a digital camera reference design using the 5 megapixel CMOS sensor and 7-inch LCD modules on the VEEK-MT (MTLC+DE2-115). The CMOS sensor module sends the raw image data to FPGA on the DE2-115 board, the FPGA on the board handles image processing part and converts the data to RGB format to display on the LCD module.
  • Page 32 User could disable this functionality by modifying the related register value being written to CMOS controller chip. Figure 4-11 Block Diagram of the Digital Camera Design  Demonstration Source Code  Project directory: Camera  Bit stream used: Camera.sof MTLC User Manual www.terasic.com May 22, 2014...
  • Page 33 KEY[2] Trigger the Image Capture (take a shot) KEY[3] Switch to Free Run mode Off: Extend the exposure time SW[0] On: Shorten the exposure time Mirror mode SW[17] HEX[7:0] Frame counter (Display ONLY) MTLC User Manual www.terasic.com May 22, 2014...

  • Page 34: Video And Image Processing For Camera

    These functions allow you to fully integrate common video functions with video interfaces, processors, and external memory controllers. The example design uses an Altera Cyclone® IV E EP4CE115F29 featured on the VEEK-MT (MTLC+DE2-115). A video source is input through the CMOS sensor on VEEK-MT which generates a digital output in RGB format.
  • Page 35  Demonstration Source Code  Project directory: VIP_Camera  Bit stream used: VIP_Camera.sof  Nios II Workspace: VIP_Camera \Software  Demonstration Batch File Demo Batch File Folder: VIP_Camera\demo_batch The demo batch file includes the following files: MTLC User Manual www.terasic.com May 22, 2014...
  • Page 36 (1).Execute VIP_Camera\demo_batch\VIP_CameraA.bat will download .sof and .elf files. (2).You may need additional Altera VIP suite Megacore license features to recompile the project. Figure 4-14 illustrates the setup for this demonstration. Figure 4-14 Setup for the VIP_Camera demonstration MTLC User Manual www.terasic.com May 22, 2014...

  • Page 37: Digital Accelerometer Demonstration

    Light Photo Sensor. The LCD displays the interface. When tilting the VEEK-MT (MTLC+DE2-115), the ADXL345 measures the static acceleration of gravity. In the Nios II software, the change of angle in the x-axis and y-axis is computed, and shown as angle data in the LCD display.
  • Page 38 80º in Y-axis, or from 10ºto 80º and from -80º to -10º in Y-axis, the image will invert Figure 4-16 shows the demonstration in action. Figure 4-16 Digital Accelerometer Demonstration Note: Execute G_sensor \demo_batch\test.bat to download .sof and .elf files. MTLC User Manual www.terasic.com May 22, 2014...

  • Page 39: Chapter 5 Appendix

    Change Log V1.0 Initial Version (Preliminary) Copyright © 2014 Terasic Technologies. All rights reserved. We will continue to provide interesting examples and labs on our MTLC webpage. Please visit mtlc.terasic.com for more information. MTLC User Manual www.terasic.com May 22, 2014...

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