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Terasic MTL2 User Manual

Multi-touch lcd module second edition
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Summary of Contents for Terasic MTL2

  • Page 2: Table Of Contents

    CONTENTS Chapter 1 Introduction ........................3 1.1 About the Package ............................3 1.2 External Power Supply for MTL2 ......................4 1.3 Assembly ..............................5 1.4 Connectivity ............................... 6 1.5 Getting Help ............................... 7 Chapter 2 Architecture of MTL2 ....................... 8 2.1 Features...............................
  • Page 3 5.3 Demonstration for Terasic DE2-115 FPGA Board ................... 28 5.4 Demonstration Source Code ........................30 Chapter 6 Appendix ........................31 6.1 Revision History ............................31 6.2 Copyright Statement ..........................31 MLT2 User Manual www.terasic.com April 12, 2016...

  • Page 4: Chapter 1 Introduction

    FPGA applications and provides five points multi-touch gesture support. An IDE cable with an IDE to GPIO (ITG) adapter is used to interface with various Terasic FPGA development boards through a 2x20 GPIO interface on the MTL2. The kit contains complete reference designs and source code for an ePhoto demonstration and Painter application.

  • Page 5: External Power Supply For Mtl2

    Figure 1-1 Contents of MTL2 Kit Figure 1-2 shows the power adapter for the MTL2. Due to the fact that the LCD panel in the MTL may consumes more power than some FPGA boards can provide. a dedicated power adapter...

  • Page 6: Assembly

    Figure 1-3 External USB Power Connection Setup Here are the procedures to assemble the MTL2 kit: Connect the IDE cable to the IDE connector on the back of the MTL as shown in the Figure 1-4. MLT2 User Manual www.terasic.com...

  • Page 7: Connectivity

    Figure 1-4 MTL connection for the IDE cable Place four silicon footstands to foot pegs of the MTL2 as shown in Figure 1-5. Figure 1-5 MTL2 Footstand Setup The following figures show the connectivity for MTL2 to DE2-115 and DE1-SoC FPGA Development Boards.

  • Page 8: Getting Help

    Figure 1-6 MTL2 with DE2-115 Figure 1-7 MTL2 with DE1-SoC Here is information of how to get help if you encounter any problem:  Office Hours: 9:00 a.m. to 6:00 p.m. (GMT +8)  Telephone: +886-3-550-8800  Email: support@terasic.com MLT2 User Manual www.terasic.com...

  • Page 9: Architecture Of Mtl2

    Chapter 2 Architecture of MTL2 This chapter provides information regarding features and architecture of the MTL2. The key features of this module are listed below:  800x480 pixel resolution LCD with 24-bit color depth  Five-point touch support  Gesture support ...
  • Page 10 Figure 2-1 MTL2 Top View The bottom view of MTL2 is shown in Figure 2-2. It depicts the layout and indicates the locations of connectors and key components. Figure 2-2 MTL2 Bottom View MLT2 User Manual www.terasic.com April 12, 2016...
  • Page 11 Figure 2-3 shows the block diagram of MTL2. The IDE connector houses all the wires from peripheral interfaces, connecting to the FPGA of a development kit through the IDE cable and ITG adapter. Figure 2-3 Block Diagram of MTL2 Figure 2-4 illustrates the connection for MTL2 to the Terasic FPGA boards.

  • Page 12: Ide Cable

    The connection cable included is a standard IDE cable. However, to achieve the best performance, we strongly recommend users use the bundled IDE cable only. Third-party IDE cables may cause the MTL2 to malfunction, or even damage the module. The IDE cable is shown in Figure 2-5.
  • Page 13 Figure 2-6 ITG Adapter (Top View) Figure 2-7 ITG Adapter (Bottom View) MLT2 User Manual www.terasic.com April 12, 2016...

  • Page 14: Using The Mtl2

    Chapter 3 Using the MTL2 This chapter provides information on how to control the MTL2 hardware, including definition of 2x20 GPIO interface, LCD control, and multi-touch control signals. The 2x20 GPIO female connector is designed to directly connect to the 2x20 GPIO male connector on the Terasic FPGA development boards.
  • Page 15 MTL_B[2] Output 3.3-V LVTTL MTL_B[3] Output 3.3-V LVTTL MTL_B[4] Output 3.3-V LVTTL MTL_B[5] Output 3.3-V LVTTL MTL_B[6] Output 3.3-V LVTTL MTL_B[7] MTL_HSD Output 3.3-V LVTTL MTL_VSD Output 3.3-V LVTTL MTL_TOUCH_I2C_SCL Output 3.3-V LVTTL MLT2 User Manual www.terasic.com April 12, 2016...

  • Page 16: Using Lcd

    Typical Value Item Symbol Unit Min. Typ. Max. Vertical Display Area VS period time 510 525 650 TH VS pulse width tvpw 20 TH VS Blanking 23 TH HS Front Porch tvfp 147 TH MLT2 User Manual www.terasic.com April 12, 2016...

  • Page 17: Using Terasic Multi-Touch Ip

    Figure 3-2 Horizontal input timing waveform Figure 3-3 Vertical input timing waveform Terasic Multi-touch IP is provided for developers to retrieve user inputs, including multi-touch gestures and single-touch. The file name of this IP is i2c_touch_config.v, which is located in System CD \IP folder.
  • Page 18 When the oREADY rises, it indicates touch activity, and the associated information can be collected from the oREG_X1~ oREG_X5, oREG_Y1~ oREG_Y5, oREG_TOUCH_COUNT, and oREG_GESTURE pins. Figure 3-4 Signaltap II Waveform for Multi-Touch IP MLT2 User Manual www.terasic.com April 12, 2016...
  • Page 19 Table 3-4 Definition of Terasic Multi-touch IP Signals Pin Name Direction Description iCLK Input Connect to 50MHz clock iRSTN Input Connect to system reset signal INT_n Input Connect to interrupt pin of touch IC oREADY Output Triggered when the data of following six...
  • Page 20 Zoom In 0x48 Zoom Out 0x49 No Gesture 0x00 Note: The Terasic IP Multi-touch IP can also be found under the \IP folder in the system CD, as well as the reference designs. MLT2 User Manual www.terasic.com April 12, 2016...

  • Page 21: Chapter 4 Ephoto Demonstration

    Chapter 4 ePhoto Demonstration This chapter describes how to use MTL2 to design a simple HDL code to implement a photo viewer. The demonstration can support the following Terasic FPGA boards:  DE2-115 This demonstration implements a simple photo viewer. Before running this demonstration, three 800x480 photos should be vertically merged into one 800x1440 photo and be stored in FLASH of the FPGA board in advance.

  • Page 22: Block Diagram Of The Ephoto Design

    Zoom handles the photo zooming process. The displayed photo is zoomed before being sent to the LCD display. When users touch the MTL2 screen, I2C Touch Config will receive an interrupt signal from the touch screen. When an interrupt is detected, I2C Touch Config will read touch information from the touch panel and assert the oREADY signal.

  • Page 23: Loading Photos Into Flash

    6. Click on the “Write a File to FLASH” button. When the Control Panel responds with the standard Windows dialog box and asks for the source file, select the “DEMO.raw” file in the “Demonstrations\RTL\Photo” directory 7. When loading is completed, a prompt will appear indicating success. MLT2 User Manual www.terasic.com April 12, 2016...

  • Page 24: Demonstration For Terasic De2-115 Fpga Board

    This section shows how to setup the painter demo on the Terasic DE2-115 FPGA Board. For other Terasic FPGA boards, the setup procedures are similar. The demonstration configuration is as shown in Make sure the ITG adapter is connected firmly to the IDE cable. Plug the ITG adapter into the GPIO-0 header of the FPGA development kit from MTL2 before turning on.

  • Page 25: Custom Display Photo

    Procedure for creating custom photos for ePhoto: 1. Prepare three 24-bit bitmap format photos with image resolutions of 800 (width) x 480 (height) pixels for each, as shown in Figure 4-6. Figure 4-6 Original Photo Resolution MLT2 User Manual www.terasic.com April 12, 2016...
  • Page 26 3. Use the tool “bmp_to_raw.exe” in the “Demonstrations\RTL\Photo” directory to convert the picture to raw file. This tool will removing bmp file header that help flash controller read the correct file data. Figure 4-7 Photo Format for the ePhoto Demonstration MLT2 User Manual www.terasic.com April 12, 2016...

  • Page 27: Chapter 5 Painter Demonstration

    SOPC Builder and the Altera’s Video and Image Processing Suite (VIP). The design demonstrates how to use multi-touch gestures and single-touch. The demonstration requires the following hardware:  Terasic FPGA Board  Multi-touch LCD Module Figure 5-1 shows the Graphical User Interface (GUI) of the Painter Demo. The GUI is classified into four separate areas: Painting Area, Gesture Indicator, Clear Button, and Color Palette.

  • Page 28: System Description

    VIP Video Out is used to display the display content. The display content is drawn by the NIOS II processor according to user input. For multi-touch processing, a Terasic Memory-Mapped IP is used to retrieve the user input, including multi-touch gestures and single-touch coordinates. For IP--usage details please refer to the Chapter Three in this document.

  • Page 29: Demonstration For Terasic De2-115 Fpga Board

    Figure 5-3 System Block Diagram This section shows how to setup the painter demo on the Terasic DE2-115 FPGA Board. For other Terasic FPGA boards, the setup procedures are similar. Figure 5-4 Hardware Setup with DE2-115 MLT2 User Manual www.terasic.com...
  • Page 30 Figure 5-5 Hardware Setup with DE1-SoC Figure 5-6 Hardware Setup with DE0-Nano Figure 5-7 Hardware Setup with DE0-CV MLT2 User Manual www.terasic.com April 12, 2016...

  • Page 31: Demonstration Source Code

    System CD onto your system and execute “test.bat”. 7. Now, you should see the painter GUI on the LCD. The source code locations of this demonstration for the various Terasic FPGA boards are shown in Table 5-1. Note: The project is built under Quartus II 13.1, and both Altera VIP license and Terasic Multi-Touch IP license are required for rebuilding the project.

  • Page 32: Chapter 6 Appendix

    Modify Figure 5-7 V1.0.3 Modify Figure 5-7 change DE0-nano-soc to DE0-nano Copyright © 2016 Terasic Technologies. All rights reserved. We will continue to provide interesting examples and labs on our MTL2 webpage. Please visit mtl2.terasic.com for more information. MLT2 User Manual www.terasic.com...
  • Page 33 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Terasic P0189...

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