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SD-AT1000
R-CH
1
1
1
A_GND
3
2
2
L-CH
4
3
3
D_GND
5
4
4
H.P SW
6
5
5
RIN
3
LIN
4
ROUT1
5
LOUT1
6
ROUT2
7
LOUT2
8
ROUT3
9
LOUT3
10
SW
CENTER
D_+5V
+B
13
PROTECT
1
L_MUTE
27
W_S_MUTE
26
F_S_MUTE
25
C_S_MUTE
24
S_S_MUTE
23
S_MUTE
22
FUN_LOCK
21
PROTECT
20
+B_CHECK
19
18
17
A/D_RESET
16
OFFSETPROTECT
15
CCB_CE
14
CCB_DO
13
CCB_CL
12
CCB_DI
11
P_CONT_LEVEL
10
H.P_SW
9
VOL_DA
8
VOL_CL
7
BASS_SW
6
CONFIG
5
9V
A_+9V
4
D_+5V
3
GND(U-COM)
2
UCON5V
1
CNP501
A_+9V
A_+9V
11
PROTECT
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R_CH
A_GND
L_CH
D_GND
H.P SW
CONFIG
Q528
Q501
Q502
24 23 22 21
19
17
IN2MIX
25
IN DSPSR
26
IN DSPSL
27
INDSPC
28
IN DSPSW
29
AGND1
32
AGND2
35
OUTSW
36
OUTC
37
OUTSL
38
OUTSR
AGND3
41
44 45 46 47
48 49 50 51 52 53 54 55
D537
D538
Figure 12 BLOCK DIAGRAM (1/10)
JT501
LINE1 INPUT/
OUTPUT TERMINAL
IC520
TJM4558CD
OPE AMP.
16
15
14
13
11
10
9
8
7
4
3
2
1
IN31
IN22
80
IN21
79
TUN_R
IN12
78
TUN_L
IN11
77
ROUT32
76
ROUT31
75
IC501
BD3811K1
VOLUME IC
AGND10
70
AGND9
67
57
– 12 –
JT502
LINE2/LINE3
INPUT TERMINAL
Q531
Q532
MON_OUTL
5 6 7 8
–
+
+
+12V
+12V
–
4 3
1
Q504
5 6
IC505
–
+
NJM4565M
– +
BUFFER AMP.
4 3 2
Q503
OUTSR_LCH
OUTSR_RCH
OUTC
OUTSW
L_
Q533
7 8
1
Q599
Q598
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