Block Diagram (5 Of 7) - Panasonic TX-32LXD500 Service Manual

10.5. Block Diagram (5 of 7)

CI SLOT
(COMMON
INTERFACE)
JK8401
Vpp1,Vpp2 18 52
XV-BOARD
VCC 17 51
2 6
DATA
D0~D7
30 32
IC8410,IC8411
BUFFER
8
ADDRESS
A0~A14 10 14
21 29
RESET 58
5V 20
REG# 61
CE1#,CE2# 7 42
CONTROL
15
OE#,WE# 9
44 45
IORD#,IOWR#
IC8213
IREQ# 16 BUFFER
CD1#,CD2# 36 67
CONTROL
57 59
MCLK0,WAIT#
IC8412
MOVAL,MOSTRT 62 63
BUFFER
MDO3~MDO7 37 41
DATA
MDO0~MDO2 64 66
STROUT
46
MISTRT
3.3V 20
47 50
MDI0~MDI7 SPDATA0~7
53 56
MIBAL,MCLKI
19 20
SPEN,SPCLK
IC8003
COFDM DEMODULATOR
TU8001 23
STROUT
DVB TUNER
34
D0
SCL 18 SCLT
D3 31
4
SDA 19 SDAT
5
IMM
IFD1
9 COFDM
FEC
11 ADC
IMP Core
10
IFD2
10
IF_AGC 16 AGC1
9
D4 29
ANT_V_SUPPLY
1 D7 25
V_SUPPLY
7
CLKOUT
36
D/#P 38
RESET 12
SCL 20
SDA 21
LOCK/OP2
42
X8003
24.167MHz
62 XTALI
63
XTALO
1.8V
3.3V
TX-26/32LXD500 TX-26/32LX500F/P
Block Diagram (5 of 7)
37 38
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IC8402 IC8019
64M CPU FLASH ROM
DATA BUFFER
ED16-ED23
WP ,WE,CE,OE
DG0-DQ15
3.3V
A0-A21
5V
RESET
3.3V
EA1-EA15
IC8404
CONTROL BUFFER
5V 20
XCD1,XCD2,XWAIT,XIREQ
CHCLK,CHVAL,CHSYNC
3.3V 20
DATA
SPPKTST
IC8408
TS BUFFER
5V 20
IC8409
TS BUFFER
5V 20
SPCLK
SPEN
XFERSTO
XIRQ1
IC8501
IC8864
VCXO 27MHz
AVR +1.8V 3.3V
6
1 VOUT VIN 7
2
1
3.3V 14
39 40
IC8401
CARD 5V
OUT IN
6 7
OUT
8
EN
LOGIC,
1 CIPOWER
CHARGE IC8013
FLG
XIRQ2
PUMP 2
HDSL PEAKS_Lite
XECSO-XECS5
CONTROL BUS
BOOTSWAP ,XEDK
ELLK,XEWE2,XEWE3
XERE,ERXW
DATA BUS
ED16 NOR FLASH ROM
I/F
ED31
ADDRESS BUS EA0
EA24
CIRESET
XIORD,XIOWR
XWE,XOE,REG CI I/F
XECS3
XIREQ
XIREQ
AUDIO
XWAIT
XWAIT OUTPUT
XCD2
I/F
XCD2
XCD1
XCD1
CHCLK
HSCLKIN
CHVAL
HSVALIN
CHSYNC AV
HSSYNCIN
DECORDER VIDEO
HSDIN0 OUTPUT
I/F
TRANSPORT
HSDIN7
DECORDER
SCHDATA0
XFERSTO
XFERSTO
SPEN
ENABLE0
SPPKTST
CHPSYNC0
SPCLK
SCHCLK0
DDR-
SDRAM
XECSO,XERE
SCL1
SDA1
XIRQ1
CK27
X8006
27M
VC27
41 42
31
TX-32LXD500 / TX-26LXD500 / TX-32LX500F / TX-32LX500P / TX-26LX500F / TX-26LX500P
SBO1
SBO1
SBI1
SBI1
IC8029
IC8031
SBO1
AUDIO DAC OP AMP SBI1
8
2
DACCK 1 MCLK
1
SRCK 2 11
BICK AOUTL
DMIX 3 SDTI
4 10
LRCK LRCK AOUTR
7
XDACRST 5 PDN 14 6
9
CVBS Q8101
MVY0 MVY0 MVY7
MVY7
MVC0
MVC0 MVC7
MVC7
MHSYNC0
MVSYNC0
MVCLK0
IC8009
256M DDR_SDRAM
MMDQ0
DATA BUS
MMDQ31
MMA0
ADDRESS BUS
MMA13
CONTROL BUS
IC8024
XEWE2,PWP
2.5V DC-DC CONV.1.2V
VDD12 2 VIN 1
SW
IC8034 PVIN 8
3 FB
AVR +2.5V
4
INV
VDDQ
AVDD 4 VOUT CTL 1
VDD33 VCC 2
IC8023
AAVDD
DAVDD
DC-DC CONV.3.3V
MAVDD
SVAVDD
MVAVDD 2 SW VIN 1
IC8043
FB
3 PVIN 8
RESET
4 INV
4 OUT VDD 2
IC8042
RESET
1 VOUT VDD 2
XRST
TX-26/32LXD500 TX-26/32LX500F/P
Block Diagram (5 of 7)
43 44
TO DG1
XV01
13
A 9V
14 SUB 5V
18
SBO1(SBI1)
19 SBI1(SBO1)
22 XRST
41 DL(BS_L)
43 DR(BS_R)
SUB 9V
51
52 SUB 9V
53 SUB 9V
54 SUB 5V
57 SUB 5V
72 CVBS
88
MVY0
96 MVY7
97
MVC0
105 MVC7
107 MHSYNC0
106 MVSYNC0
MVCLK0
109
45