ICS -130 Operating Manual page 27

SA64BAR:
Slave A64 Base
Address Register
MA64BAR
Master A64 Base
Address Register
VINT:
VMEbus Interrupter
Request Register
VREQ: VMEbus
Requester Register
DOC E10523 Rev.D
(will not respond), and enabled when set to '1'.
MODE<9> When set to '0', the SCV64 Master operates in A32 or A64 mode (as
determined by MODE<20>), and in A24 mode when set to '1'.
MODE<0> If set to '0', all Slave images of the SCV64 are disabled. IN THIS
EVENT, THE ICS-130 CANNOT BE ACCESSED UNTIL A VMEBUS
RESET OCCURS.
0x40 This register sets bits 63-32 of the VMEbus A64 slave base address. The
remaining bits (31-0) are taken from the A32 image. Before accessing this
register, MODE<12> must be set to '1'. After accessing this register, MODE<12>
should be cleared.
0x44 This register sets bits 63-32 of the VMEbus A64 master base address. The
remaining bits (31-0) are taken from the A32 image. Before accessing this
register, MODE<12> must be set to '1'. After accessing this register, MODE<12>
should be cleared.
0x8C The least significant three bits (D2:0) set the interrupt level of generated by the
SCV64. Programming D3 high enables the interrupt. This bit is reset when the
interrupt is acknowledged. Caution: Changing the interrupt level while D3 is in the
enable state may cause improper operation.
0x90 The following describes the contents of VREQ:
VREQ<7> VMEbus Ownership Timer Enable. Condition 1 after reset. 0 =
Disable Timer, 1 = Enable Timer.
VREQ<6> Bus Clear Recognition Control. Condition 0 after reset. 0 = Ignore
BCLR* signal. 1 = Release bus if BCLR* asserted.
VREQ<5> VMEbus Release Mode Control. Condition 1 after reset. 0 = Release
on Request (ROR), 1 = Release when Done (RWD).
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