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ICS -130 Operating Manual

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The information in this manual has been carefully checked and is believed to be reliable; however, no
responsibility is assumed for possible inaccuracies or omissions.
reserves the right to make changes to products herein described to improve reliability, function, or design. No
patent rights are granted to any of the circuits described herein.
Extra copies of this manual are available from the factory.
DOC E10523 Rev.D
ICS-130
OPERATING MANUAL
Interactive Circuits And Systems Ltd.
November 2000
Interactive Circuits and Systems Ltd.
ICS Ltd
5430 Canotek Road
Gloucester, Ontario
K1J 9G2 Canada
http://www.ics-ltd.com
support@ics-ltd.com
Tel: (613) 749-9241
USA: (800) 267-9794
Fax: (613) 749-9461

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  • Page 1 ICS-130 OPERATING MANUAL Interactive Circuits And Systems Ltd. November 2000 The information in this manual has been carefully checked and is believed to be reliable; however, no responsibility is assumed for possible inaccuracies or omissions. Interactive Circuits and Systems Ltd.
  • Page 2 DOC E10523 Rev.D...

  • Page 3: Table Of Contents

    TABLE OF CONTENTS INTRODUCTION References GENERAL DESCRIPTION Board Specifications DETAILED DESCRIPTION ADC Section Input Bandwidth and Sample Rate Clock/Trigger Options Data Path Selection Modes of Operation VMEbus Interface Cascading Multiple Boards FPDP Interface Light-Emitting Diodes HARDWARE PREPARATION System Configuration Jumper and Switch Settings 4.2.1 VMEbus Base Address Selection 4.2.2...
  • Page 4 5.7.3 CR<2> - Diagnostic Mode Enable 5.7.4 CR<3> - P2 Enable 5.7.5 CR<4> - FPDP Enable 5.7.6 CR<5> - FPDP Word Width 5.7.7 CR<6> ADC Sampling Master Enable 5.7.8 CR<7> - ADC Clock Termination 5.7.9 CR<8> - FPDP Master Enable 5.7.10 CR<9>...

  • Page 5: Introduction

    1. INTRODUCTION The ICS-130 is a 32-channel, 16-bit, VMEbus data acquisition card with an output rate of 1.2 MSample/sec. The board offers multiple options for generating and moving data at high speed. This design has been optimized for applications which demand high speed, precision and ease of integration.

  • Page 6: General Description

    2. GENERAL DESCRIPTION Figure 1 shows a simplified block diagram of the ICS-130 board. The board uses 32 16-bit Sigma-Delta ADCs (Analog Devices AD7723) to provide simultaneous sampling at rates of up to 1.2 Msamples/sec. on each channel. The oversampling ratio of the Sigma-Delta ADC can be selected as 16 or 32.
  • Page 7 Figure 1 - ICS-130 Simplified Block Diagram © Interactive Circuits And Systems Ltd. 2000 DOC E10523 Rev.D...

  • Page 8: Board Specifications

    2.1 Board Specifications Analog Input No. of Analog Input Channels: 4, 8, 16 or 32 differential Input Impedance: 10 kOhm (each wire) Full Scale Input: 2 Vpp diff. or 4 Vpp single-ended Max. Input Sample Rate (Fs): 19.2 MHz Oversampling Ratio: 16 or 32 Max.

  • Page 9: Detailed Description

    3. DETAILED DESCRIPTION 3.1 ADC Section The ICS-130 board uses 32 16-bit Sigma-Delta ADCs (Analog Devices's AD7723). The maximum input clock for the Sigma-Delta ADC is 19.2 MHz. Thus, the maximum output rate (16x oversampling ratio mode) is 1.2 MSamples/sec. When the internal programmable frequency clock is used, the minimum sampling rate for the ADCs is 1.0 MHz.

  • Page 10: Input Bandwidth And Sample Rate

    Figure 3 - Lowpass and Bandpass (oversampling) ratio may be selected using response options the ADC Mode field of the ICS-130 Control register (see section 5.7.11). Further details on the converter characteristics are available from the manufacturer, Analog Devices, at the following web site address: http://products.analog.com/products/info.asp?product=AD7723...

  • Page 11: Clock/Trigger Options

    3.3 Clock/Trigger Options The ICS-130 offers a number of clock and trigger options. The card has an internal sampling clock provided by a programmable oscillator giving a resolution of less than 250Hz at the output rate over the entire 1.0 MHz to 19.2 MHz range. Alternatively, an external sampling clock applied at pin 25 of the P4 front panel connector may be used.

  • Page 12: Vmebus Interface

    = n * acquisition count In the capture mode with pre storage, the ICS-130 memory is used as a circular buffer of programmable length. The ICS-130 is “armed” by the user, and the control logic continuously fills the circular buffer with fresh data samples in anticipation of the trigger signal.

  • Page 13: Cascading Multiple Boards

    Master/slave status can be programmed in the Control Register (see 5.8). The 20 pin header on the front panel of the ICS-130 provides access to all signals necessary for multi card synchronization. Details of the P4 pinout are given in appendix 6.3. The term Master in this context should not be confused with VMEbus bus mastership.

  • Page 14: Fpdp Interface

    3.8 FPDP Interface A connector on the front panel of the ICS-130, designated P3, is compatible with the ICS FPDP Interface. The ICS Front Panel Data Port (FPDP) is an industry standard interconnection for board to board or system to system data transfer. This interface standard has gained acceptance in the industry for use in a broad range of signal processing applications.
  • Page 15 VME Access Green Illuminated at each valid VMEbus access to ICS130 P2 Access Green Illuminated at each valid P2 access to ICS-130 FPDP Out Green Illuminated at each valid FPDP access to ICS-130 ADC Running Green Illuminated for each ADC sample acquired ©...

  • Page 16: Hardware Preparation

    ICS-130 will be installed. All unused slots between slot 1 and the slot where the ICS-130 is installed must be jumpered to ensure correct operation.
  • Page 17 LED 1 LED 4 K10385-2 Figure 3 - ICS-130 Switch and Jumper Locations © Interactive Circuits And Systems Ltd. 2000 DOC E10523 Rev.D...

  • Page 18: Jumper And Switch Settings

    Mid-slaves, End-Slave, DSP). If FPDP is not being used, the position of the DSP board/s in the chassis with respect to the ICS-130 boards is not important, however it is recommended that the ICS-130 boards are installed in adjacent slots.
  • Page 19 The A24 base address is set as follows: Jumper VME A24 Address Bit JP1-1 JP1-2 JP1-3 JP1-4 JP1-5 In A32 mode, the user may specify the values of A31 to A27, allowing the base address to be set to any value between 0x08000000 and 0xF8000000, in increments of 0x8000000. The A32 base address is set as follows: Switch VME A32 Address Bit...

  • Page 20: P4 Local Bus Interface

    4.2.2 P4 Local Bus Interface Switch block SW3 is used to connect parallel (pull-up/pull-down) resistive terminations to the External Clock and Trigger signals, as shown in the following table. These are required if the user chooses not to use serial terminating resistors at the signal transmitter/s. Other functions of the P4 Local Bus can be programmed by software using the Control Register (see section 5.7).

  • Page 21: Programming Model

    VMEbus interface. All control register bits that are not defined have no effect on the operation of the ICS-130, but will always be read as zero. All other bits are undefined, and may be read as zero or one.
  • Page 22 WRITE ONLY ADC_CLOCK FPDP DATA BASE + 0 x 50024 WRITE ONLY FPDP_CLOCK BOARD_ADDRESS FRAME_LENGTH BASE + 0 x 58000 READ / WRITE MASTER_CONTROL K10385B3 Figure 4 - ICS-130 Register Map © Interactive Circuits And Systems Ltd. 2000 DOC E10523 Rev.D...

  • Page 23: Scv64 Registers

    The SCV64 has two sets of address and data busses, one connected to the VMEbus and the other to the ICS-130 local bus. VMEbus accesses are mapped from VMEbus space to local bus according to the programming of the SCV64.
  • Page 24 0x0C The following describes the bits of the SCV64 Control and Status Register used by the ICS-130. All other bits should be set to 0 during a write. The register Control and Status should always be cleared before starting to set up a DMA transfer.
  • Page 25 MODE: 0x3C The following describes the bits of the SCV64 Mode Control Register which may need to be accessed when using the ICS-130. All other bits should be set to '0' Mode Control Register during a write. © Interactive Circuits And Systems Ltd. 2000...
  • Page 26 SA64BAR and MA64BAR registers (see decriptions below). MODE<10> When set to '0' the VMEbus Slave image of the ICS-130 is disabled (will not respond), and enabled when set to '1'. © Interactive Circuits And Systems Ltd. 2000...
  • Page 27 When set to '0', the SCV64 Master operates in A32 or A64 mode (as determined by MODE<20>), and in A24 mode when set to '1'. MODE<0> If set to '0', all Slave images of the SCV64 are disabled. IN THIS EVENT, THE ICS-130 CANNOT BE ACCESSED UNTIL A VMEBUS RESET OCCURS. SA64BAR: 0x40 This register sets bits 63-32 of the VMEbus A64 slave base address.
  • Page 28 VREQ<4> VMEbus Request Mode Control. Condition 1 after reset. 0 = Fair, 1 = Demand. VREQ<3:2> VMEbus Ownership Timer (Time-out Period). Condition 3 after reset. 0=Zero, 1=2microsec, 2=4microsec, 3=8microsec. VREQ<1:0> VMEbus Request Level. Condition 3 after reset. 0 = Level Zero. ©...

  • Page 29: Performing Block Transfers

    ADC data window, whichever is smaller. For VME Master transfers, the count is specified in (32 bit) longwords. Note that the VMEbus specification limits block transfers to a maximum of 256 Bytes, however, the ICS-130 design does not prevent transfers of larger blocks as described above.

  • Page 30: Vmebus Dma Slave

    5.4 ADC Data This section of the ICS-130's VMEbus memory map is used to read data from the ADC memory over the VMEbus. The VMEbus ADC Data area is 0x40000 bytes (256KB) in size.

  • Page 31: Status Register (Sr)

    Mask register (IMR) are set. The status register should be used to determine the interrupt status of the ICS-130, and the source of the interrupt. If an interrupt is masked in the IMR, the status of the associated event may still be read here.

  • Page 32: Sr<2> - P2 Irq

    P2 Module is asserting IRQ 5.5.4 SR<3> - IRQ This bit indicates that the ICS-130 is asserting a VMEbus interrupt from either source (i.e. Master transfer completion or ADC Swing Buffer swap). It is therefore an OR of the state of bits 0 and 1 of this register.

  • Page 33: Interrupt Mask Register (Imr)

    5.6 Interrupt Mask Register (IMR) Read/Write The Interrupt Mask register is used to enable and disable VMEbus interrupts. The status of masked interrupts may be read in the corresponding bits of the status register, but no interrupt will occur even when the interrupt is asserted. 5.6.1 IMR<0>...

  • Page 34: Control Register (Cr)

    5.7 Control Register (CR) Read/Write The Control Register controls the overall configuration of the ICS-130. 5.7.1 CR<0> - Trigger Select This bit determines if the external ADC Trigger is used to start an acquisition. When using an external trigger, triggering occurs following the rising edge of the trigger signal. The signal must remain high for at least one complete acquisition (clock) cycle.

  • Page 35: Cr<2> - Diagnostic Mode Enable

    5.7.3 CR<2> - Diagnostic Mode Enable This bit is used to enable the Diagnostic mode. In this mode, VMEbus Data can be written to the swing buffer. Once cleared, the data can be read back from the swing buffer. CR<2> Diagnostics enable READ/WRITE Diagnostic Mode disabled...

  • Page 36: Cr<5> - Fpdp Word Width

    This bit selects the board as a Sampling Master or Slave, when operating in a multiple ICS-130 board acquisition cluster. In the cluster, only one board can be set as Master. The Master board sends to all slaves the ADC_CLK (pin 1 and 2 on the P4 connector) and the Trigger signal (pin 10 on the P4 connector).

  • Page 37: Cr<7> - Adc Clock Termination

    Slaves receive the FPDP_CLK on the P4 connector pin 12 and 13 and the Data Valid signal on pin 15. CR<8> FPDP Master Enabled READ/WRITE ICS-130 is FPDP Slave ICS-130 is FPDP Master © Interactive Circuits And Systems Ltd. 2000 DOC E10523 Rev.D...

  • Page 38: Cr<9> - Fpdp Termination

    5.7.10 CR<9> - FPDP Termination This bit enables the resistive termination on the FPDP NRDY* and SUSPEND* signals. These must be connected when using the FPDP interface, on the Master board only. This applies to single board and multiple board configurations. CR<9>...

  • Page 39: Cr<13> Trigger

    5.7.13 CR<13> - Trigger This bit is the internal trigger signal. The “enable” bit CR<14> must have been previously set, and CR<0> must be set to internal trigger. This bit is automatically cleared after acquisition is started. CR<13> Trigger READ/WRITE ** Automatically cleared ** Begin acquisition 5.7.14 CR<14>...

  • Page 40: Buffer Length Register

    The Buffer Length register is used to determine the number of samples stored in the ICS-130 Swing Buffer. The register must be programmed with the number of 32-bit words (i.e. pairs of samples) to be acquired in the buffer prior to each interrupt or to completion. In continuous mode, the 19-bit buffer length value determines the number of 32-bit words written to the swing buffer by the ADCs before the buffer banks are swapped.

  • Page 41: Decimation Count Register

    2. This feature enables the output rate to be reduced, allowing operation of the ICS-130 with an effective sample output rate below 31.25 kHz. However, the user is cautioned that decimating the output in this way counteracts the advantages of the Sigma-Delta technology of the converters.

  • Page 42: Fpdp Clock Frequency Register

    Strobe frequency used. 5.15 Arm Register Write Only Writing to this register initiates pre-storage of data when the ICS-130 is used in Capture mode with pre-trigger storage. See section 3.4 for details on using pre-trigger storage. 5.16 ADC Reset Register Write only A write to this register resets the ADC swing buffer memory pointers.

  • Page 43: Board Reset Register

    These bits program the FPDP address for the current board in an FPDP cluster. The range is 0 to (N-1), where is N is the number of ICS-130 boards connected on the FPDP and P4 cables. The valid range of values for this field is 0 to 31. The FPDP Master or Stand-alone Master must always have FPDP board address zero.

  • Page 44: Using Diagnostic Mode

    5.19 Using Diagnostic Mode The ICS-130 has built in digital diagnostic circuitry wich allows the user to test all functionality of the board with the exception of the ADCs themselves. This is accomplished by feeding the ICS-130 with simulated ADC data from an on-board 4 KWord FIFO memory.
  • Page 45 APPENDICES © Interactive Circuits And Systems Ltd. 2000 DOC E10523 Rev.D...

  • Page 46: Appendices

    14: If using internal trigger, set trigger bit in control register. 15: If using external trigger, expect external trigger signal/s to occur here. 16: Wait for interrupt from ICS-130 (VME/P2 output) or FPDP receiver. 17: Read back acquired data. 18: If using continuous mode: IF enough data acquired, disable acquisition.

  • Page 47: Programming The Internal Clock Generator And Fpdp Clock

    Data is transferred to the device serially; it is necessary to write the data to the ICS-130 ADC Clock register one bit at a time; bit 0 of the register is the relevant bit. Thus the programming sequence...

  • Page 48: Control Register

    6.2.3 Control Register When writing data to the Control Register, it is necessary to include a Protocol Field to identify the data as Control Register data. Protocol Field (6 bits) = 0 1 1 1 1 0 It is important that the sequence of four ones contained in the protocol field never be sent except as part of the Protocol Field.
  • Page 49 the device specification requires that a zero must be inserted in the word after each occasion when three one's have been transmitted to the device, regardless of whether the next bit is a 0 or a 1. This procedure is known as "bit stuffing". For this reason, the actual length of a programming word may vary between 22 and 29 bits.

  • Page 50: Vco Programming Constraints

    The values of the P and Q parameters must be selected so that f remains between 50 MHz and 150 MHz, inclusive. The value programmed to the M field programs a division register to allow sub-multiples of the VCO frequency to be obtained at the output; the maximum divisor possible is 128.

  • Page 51: Oscillator Programming Example

    The result: Fout = 12.8 = (2*14.31818*(P+3)/(Q+2))/2 where M = 0, 1, 2, 3, 4, 5, 6, 7 since M = 2: (P+3)/(Q+2) = 1.787936735 The two choices of P and Q giving the nearest to the required frequency are: Error (PPM) 51.19834 51.19834...
  • Page 52 programming the oscillator to an initial or new frequency is as follows: Load Control register to enable loading of the Programming word register, enable the output and select the reference frequency for output from the Internal Multiplexer. The Protocol word follows the control word. All data is shifted in LSB (Least Significant Bit) first.

  • Page 53: Analog 1-16 Connector Details

    6.3 Analog 1-16 Connector Details Connector on board: ODD44F4R7NTX Mating connector: ODD44M..(consult Manufacturer's data for details) Manufacturer: Positronics Industries Inc., (417)866-2322 SIGNAL SIGNAL CHANNEL 1- CHANNEL 1+ CHANNEL 2- CHANNEL 2+ CHANNEL 3- CHANNEL 3+ CHANNEL 4- CHANNEL 4+ CHANNEL 5- CHANNEL 5+ CHANNEL 6-...
  • Page 54 K10167-8 Figure 5 - ICS-130 Analog Connector Pinout © Interactive Circuits And Systems Ltd. 2000 DOC E10523 Rev.D...

  • Page 55: P4 Local Bus Connector Details

    6.5 P4 Local Bus Connector Details Suitable mating connectors are available from a number of manufacturers. The one listed is an example only. Connector on board: 8831E-026-170L (KEL Corporation) P50E-026P1-RR1-TG (Robinson-Nugent) Mating connector: 8825E-026-175 KEL (with strain relief) 8825R-026-175 KEL (without strain relief) P25E-026S-TG Robinson-Nugent Manufacturers: KEL Corporation, (408)720-9044...
  • Page 56 FPDP data transfers. This signal is bussed from the FPDF master to all slaves, and is driven by the master only. Digital Ground /FP_DV FPDP Data Valid. This line is asserted by the FPDP transmitter. It signals valid data on the FPDP bus. Digital Ground CHAN5 Signal used in FPDF board addressing...

  • Page 57: P3 Fpdp Details

    In other words, at the DSP connector pin 1 connects to pin 80 at the ICS-130, while pin 2 connects to pin 79 at the ICS-130. The FPDP is a high performance 32 bit parallel interface configured with a ribbon cable to connect boards or systems together.
  • Page 58 PCB AREA 79 75 80 76 BOARD CONNECTOR COMPONENT SIDE VIEW PIN 1 INDICATOR PIN 1 INDICATOR 79 77 BOARD CONNECTOR BOARD EDGE VIEW Connector row and column designations are shown outside connector outline. Cable numbers are shown inside connector outline. FPDP BOARD-MOUNTED CONNECTOR KEL 8831E-080-170L Robinson-Nugent P50E-080P1-SR1-TG...
  • Page 59 TABLE 6.3 ICS-130 FPDP P3 connector pin assignments PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL STROBE NRDY* DIR* 10 GND 11 RESERVED 12 GND SUSPEND* 14 GND 15 GND 16 GND PIO2 18 GND 19 PIO1 20 GND RESERVED 22 GND...

  • Page 60: Fpdp Signals

    6.6.2 FPDP Signals A description of FPDP signals is given in Table 6.4. Further details concerning the FPDP design are given in ICS INPUT Technical Note No.15, which is available from the factory or from the ICS Web site at: www.ics-ltd.com/technotes_white_papers.html...
  • Page 61 TABLE 6.4 FPDP Signal Descriptions Signal/s Signal Name Description D31:00 Data Bus 32 bit data bus driven by the data source. DIR* Data Direction The data source asserts DIR* low. DVALID* Data Valid When asserted, DVALID* indicates that the data bus has valid data.

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