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Rohm Kionix KX132 Getting Started

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1. Introduction
This application note will help developers quickly implement proof-of-concept designs using the
KX132 tri-axis accelerometer. Please refer to the corresponding Technical Reference Manual
document for available engines specific to your product and additional implementation guidelines.
Kionix strives to ensure that our accelerometers will meet design expectations by default, but it is not
possible to provide default setting to work in every environment. Depending on the intended
application, it is very likely that some customization will be required to optimize performance. The
information provided here will help the developer get the most out of these tri-axis accelerometers.
2. Circuit Schematic
This section shows recommended wiring for this accelerometer, based on proven operation of the
part. Specific applications may require modifications from these recommendations. Please refer to
the corresponding Product Specifications document for all pin descriptions.
36 Thornwood Dr. — Ithaca, NY 14850 USA
Tel: 607-257-1080 — Fax: 607-257-1146
www.kionix.com
—
info@kionix.com
Figure 1: KX132 Application Schematic
AN092
Getting Started
© Kionix 2019 All Rights Reserved
11 July 2019
Page 1 of 27

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Summary of Contents for Rohm Kionix KX132

  • Page 1 AN092 Getting Started 1. Introduction This application note will help developers quickly implement proof-of-concept designs using the KX132 tri-axis accelerometer. Please refer to the corresponding Technical Reference Manual document for available engines specific to your product and additional implementation guidelines. Kionix strives to ensure that our accelerometers will meet design expectations by default, but it is not possible to provide default setting to work in every environment.
  • Page 2 AN092 3. Quick Start Implementations Here we present several basic ways to initialize the part. These can vary based on desired operation, but generally the initial operations a developer wants to do are: 1) read back acceleration data asynchronously, 2) read back acceleration data when next data is ready via interrupt (synchronous data reading), 3) use of the sample buffer, 4) use the Wake-Up function, 5) activate the tilt position function, 6) activate the tap/double-tap function, and 7) activate the free-fall function.
  • Page 3 AN092 3.2. Synchronous Reading (with hardware interrupt) This example configures and enables the accelerometer to start outputting sensor data with a synchronous signal (DRDY) and data can read from the output registers. Write 0x00 to Control 1 (CNTL1) to set the accelerometer in stand-by mode Register Name Address Value...
  • Page 4 AN092 3.3. Synchronous Reading (without hardware interrupt) This example configures and enables the accelerometer to start outputting sensor data with a synchronous signal (DRDY) and data can read from the output registers. Write 0x00 to Control 1 (CNTL1) to set the accelerometer in stand-by mode Register Name Address Value...
  • Page 5 AN092 3.4. Sample Buffer Operation 3.4.1. Buffer Full Interrupt (BFI) This example configures enables the accelerometer to start outputting sensor data to the internal buffer until full. When the buffer is full, a hardware interrupt is generated and data can then be read from the buffer.
  • Page 6 AN092 data samples. (Note: With BRES=0 (8-bit resolution), in BUF_CNTL2, it is possible to collect 171 samples or 513 bytes of data). 3.4.2. Watermark Interrupt (WMI) This example configures enables the accelerometer to start outputting sensor data to the internal buffer until a watermark is reached. When the watermark is reached, a hardware interrupt is generated and data can then be read from the buffer.

  • Page 7: Trigger Mode

    AN092 Once a Buffer-Full Interrupt is issued on INT1 pin, acceleration data can then be read from the Buffer Read (BUF_READ) register at address 0x63 in 2’s complement format. The data is recorded in the following order: X_L, X_H, Y_L, Y_H, Z_L and Z_H (16-bit mode) with the oldest data point read first as the buffer is in FIFO mode.
  • Page 8 AN092 Register Name Address Value BUF_CNTL2 0x5F 0xE2 Write 0x3F to Interrupt Control 2 (INC2) to enable all positive and negative directions that can cause a wakeup event. Register Name Address Value INC2 0x23 0x3F Write 0xAE to Control 3 (CNTL3) to set output data rate for the wakeup engine (OWUF) to 50Hz.
  • Page 9 AN092 Write 0xE0 to Control 1 (CNTL1) to set the accelerometer into operating mode (PC1=1), full power mode (RES=1), data ready enabled (DRDYE=1), range to ±2g (GSEL=0). Register Name Address Value CNTL1 0x1B 0xE0 Provide some time for the buffer to fill to the configured threshold. Assuming the default ODR was used, it should take approximately 0.86 seconds.
  • Page 10 AN092 3.5. Wake-up / Back-to-Sleep Engine 3.5.1. Wake-up This example configures and enables the accelerometer to detect wake-up events using an external interrupt pin with Back-to-Sleep function disabled. Write 0x00 to Control 1 (CNTL1) to set the accelerometer in stand-by mode Register Name Address Value...
  • Page 11 AN092 Write 0x01 to Control 5 (CNTL5) to for the sensor into sleep mode (MAN_SLEEP=1). Register Name Address Value CNTL5 0x1F 0x01 Write 0x05 to Wakeup Function Counter (WUFC) to set the time motion must be present for 0.1 second before a Wake-up interrupt is triggered. The following formula is used: WUFC (counts) = Desired Delay Time (sec) x OWUF (Hz) WUFC (counts) = 0.1 sec x 50 Hz = 5 counts Register Name...
  • Page 12 AN092 Read Interrupt Latch Release (INL_REL) to unlatch (clear) the output interrupt created by the motion detection function and to clear the WUFS bit in the Interrupt Status 3 (INS3). Register Name Address Value INT_REL 0x1A Write 0x01 to Control 5 (CNTL5) to force sleep state (MAN_SLEEP=1). With Back-to-Sleep engine disabled, this step is required in order to be able to detect additional wake-up interrupt.
  • Page 13 AN092 3.5.2. Wake-up and Back-to-Sleep This example configures and enables the accelerometer to detect both wake-up and back-to- sleep events using an external interrupt pin. Write 0x00 to Control 1 (CNTL1) to set the accelerometer in stand-by mode Register Name Address Value CNTL1...
  • Page 14 AN092 Write 0x01 to Control 5 (CNTL5) to force sleep state (MAN_SLEEP=1). Note, this also clears the WAKE bit in STAT register to indicate Back-to-Sleep state. Register Name Address Value CNTL5 0x1F 0x01 Write 0x05 to Back-to-Sleep Counter (BTSC) to set the time motion must be absent for 0.1 second before a Back-to-Sleep interrupt is triggered.
  • Page 15 AN092 Monitor the physical interrupt INT1 of the accelerometer, if the acceleration input profile satisfies the criteria previously established for the 0.5g motion detect threshold level in both positive and negative directions of the X, Y, Z axis for more than 0.1 second, then there should be positive latched interrupt present.
  • Page 16 AN092 3.6. Tilt Engine 3.6.1. Activate Tilt Position Function with Face Detect Write 0x00 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode. Register Name Address Value CNTL1 0x1B 0x00 Write 0x3F to Control 2 register (CNTL2) to enable Tilt detection from positive and negative directions of all three axes (+x, -x, +y, -y, +z, -z).
  • Page 17 AN092 Write 0x30 to Interrupt Control Register (INC1) to output the physical interrupt of the previously defined Tilt Position function. This value will create an active high and latched interrupt. Register Name Address Value INC1 0x22 0x30 Write 0x01 to Interrupt Control Register 4 (INC4) to set the Tilt Position interrupt (TPI1) to be reported on physical interrupt pin INT1.
  • Page 18 AN092 3.7. Activate Tap/Double Tap Engine Write 0x00 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode. Register Name Address Value CNTL1 0x1B 0x00 Write 0x3F to Interrupt Control 3 register (INC3) to enable tap/double tap from positive and negative directions of all three axes (+x, -x, +y, -y, +z, -z).
  • Page 19 AN092 Write 0x1A (26d) to Tap Threshold Low register (TTL). This register represents the 8-bit (0d– 255d) jerk low threshold to determine if a tap is detected. The Performance Index (PI) is the jerk signal that is expected to be greater than this threshold and less than the TTH threshold during single and double tap events.
  • Page 20 AN092 Write 0x30 to Interrupt Control Register (INC1) to output the physical interrupt of the previously defined Tap/Double-Tap function. This value will create an active high and latched interrupt. Register Name Address Value INC1 0x22 0x30 Write 0x04 to Interrupt Control Register 4 (INC4) to set the Tap/Double-Tap interrupt (TDTI) to be reported on physical interrupt pin INT1.
  • Page 21 AN092 3.8. Activate Free-fall Engine Write 0x00 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode. Register Name Address Value CNTL1 0x1B 0x00 Write 0x80 to Free-Fall Control Register (FFCNTL) to enable Free fall engine, to set Free-fall interrupt latch control, count up/down debounce methodology, and the Output Data Rate (ODR) to 12.5Hz (Default).
  • Page 22 AN092 Write 0xC0 to Control Register 1 (CNTL1) to set the accelerometer in operating mode, high performance (full power), and G-range to ±2g. Register Name Address Value CNTL1 0x1B 0xC0 Monitor the physical interrupt INT1 of the accelerometer, if the acceleration input profile satisfies the criteria previously established for the 0.5g free-fall detect threshold level in both positive and negative directions of the X, Y, Z axis for more than 0.320 second, then there should be a positive latched interrupt present.

  • Page 23: Timing Requirements

    AN092 4. Timing Requirements There are several timing requirements that developers should keep in mind when working with the KX126 accelerometer: I²C Clock - The I²C Clock can support Fast Mode up to 400 KHz and High Speed mode up to 3.4 MHz.

  • Page 24: Interrupt Configuration

    AN092 5. Interrupt Configuration The physical interrupt has 6 possible configurations, based on two states for each of the three customizable variables located in Interrupt Control Register 1: Latched/Pulsed (IEL – bit 3 – 0x08) 0 – Latched mode – When an interrupt is triggered, it will remain active on the pin until cleared.

  • Page 25: Troubleshooting

    AN092 6. Troubleshooting All Interrupt Issues Make sure the accelerometer is configured to issue interrupt signals in the way that your GPIO is programmed to handle them. An oscilloscope on the physical interrupt pin can be a valuable tool to confirm physical interrupt operation.
  • Page 26 AN092 Free fall Detect Interrupt Not Working Make sure the Free fall engine is enabled (FFIE bit in Free Fall Control Register FFCNTL) Try adjusting the threshold requirements to achieve desired operation by adjusting the threshold value in the FFTH register. If the part is generating interrupts two often, try increasing the delay/debounce time in the FFC register.
  • Page 27 AN092 8. The Kionix Advantage Kionix technology provides for X, Y, and Z-axis sensing on a single, silicon chip. One accelerometer can be used to enable a variety of simultaneous features including, but not limited to: Hard Disk Drive protection Vibration analysis Tilt screen navigation Sports modeling...