Vertex Standard VX-900 Service Manual page 19

Transmit Inhibit
When the Transmit PLL is unlocked, pin 18 of PLL
chip Q1045 goes to logic "low." The resulting DC
"unlock" control voltage is passed to pin 20 of mi-
croprocessor Q1040. While the transmit PLL is un-
locked, pin 85 of Q1040 remains low, which then
turns off the Automatic Power Controller Q1015
(PDTC144EE) and Q1013 (NJM2902V) to disable
the supply voltage to the Power Module Q1014, dis-
abling the transmitter.
Spurious Suppression
Generation of spurious products by the transmitter
is minimized by the fundamental carrier frequency
being equal to final transmitting frequency, modu-
lated directly in the transmit VCO. Additional har-
monic suppression is provided by a low-pass filter
consisting of L1004, L1005, and L1006 and C1003,
C1014, C1015, C1017, C1019, and C1020, result-
ing in more than 60 dB of harmonic suppression
prior to delivery of the signal to the antenna.
PLL Frequency Synthesizer
The PLL frequency synthesizer consists of the VCO,
Q1025 (2SC5226-4/5:RX) or Q1031 (22SC5226-4/
5:TX); VCO buffers Q1026 (2SC5226-4/5), Q1022
(2SC5225-4/5) ; PLL subsystem IC Q1045
(SA7025DK) and 21.6 MHz reference crystal X1002.
The frequency stability is ±2.5 ppm within the tem-
perature range of -30° to +60°C. The output of the
21.6 MHz reference is applied to pin 8 of the PLL IC.
While receiving, VCO Q1025 oscillates between
111.94 and 151.94 MHz according to the transceiver
version and the programmed receiving frequency.
The VCO generates at 111.94 to 151.94 MHz for pro-
viding to the first local signal. In the transmit mode,
the VCO generates 134 to 174 MHz.
The output of the VCO is amplified by Q1033, and
is routed to pin 5 of the PLL IC. Also the output of
the VCO is amplified by the Q1022 and routed to
the first local and the drive chain according
toinstructions from D1028.
The PLL IC consists of a prescaler, fractional divider,
reference divider, phase comparator, and a charge
pump. This PLL IC is a fractional-N type synthesizer
utilizing a 40 or 50 kHz reference signal which is
Circuit Description
eighth multiple of the channel step size (5, 6.25 or
7.5 kHz). The input signal from pins 5 and 8 of the
PLL IC is divided down to 40 or 50 kHz and com-
pared at the phase comparator. The pulsed output
signal of the phase comparator is applied to the
charge pump and transformed into a DC signal in
the loop filter. The DC signal is applied to the pin 1
of the VCO and locks to keep the VCO frequency
constant.
PLL data is delivered from DTA (pin 100), CLK (pin
2) and PSTB (pin 98) of the microprocessor Q1040.
The data are applied to the PLL IC when the channel
is changed or when transmission switches is changed
to reception (and vice versa). A PLL lock condition is
always monitored by the pin 20 of Q1040. When the
PLL is unlocked, the "UL" line goes low.
Miscellaneous Circuits
Push-To-Talk Transmit Activation
The PTT switch on the microphone is connected to
pin 32 of microprocessor
Q1040, so that when the PTT switch is closed, pin
85 of Q1040 goes high. This signals the micropro-
cessor to activate the TX/RX controller Q1004
(UMG2N), which then disables the receiver by in-
terrupting the 5 V supply bus at Q1009 (UN911F) to
the front-end, FM IF subsystem IC Q1038, and the
receivers VCO circuitry.
At the same time, Q1003 (XP1501) and Q1002
(CPH6102) activate the TX 5V supply line to enable
the transmitter.
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