JVC Super VHS Service Manual page 40

4.26 CAMERA AND Y/C SYSTEM BLOCK DIAGRAM
0 2 CCD
5
IC5301
Q5301
CN5301
7
OPTICAL
BUF 5
BLOCK
13
14
1
CCD
IMAGE 2
SENSOR 3
4
10
CN5301
3 9 10 11 12 1314
4
12 6 5 4 3 2 1
CN22
3
CN15
10
F_SENS
Z_SENS 20
IC4501(F/Z/I/MDA)
26
FOCUS3 8
BRIDGE
24
DRIVER
FOCUS1 5
28
FOCUS4 6 BRIDGE
30
FOCUS2 7 DRIVER
2 10
ZOOM2 1 BRIDGE
12
2 DRIVER
ZOOM4
14
ZOOM3 3
BRIDGE
16
DRIVER
ZOOM1 4
HE_IN+ 19
HE_OUT- 18
HE_IN- 17
HE_OUT+ 16
DUMP- 14
DRIVE+ 13
DUMP+
12
1
JIG_CONN.
CN25
RXD
RXD 10
TXD
TXD 20
A B
0 1 MAIN
C
IC5201
(TG/CDS)
27
(CDS/AGC/AD)
C
CN22
CCD_OUT 26 CDSIN
10 A/D
28 CDS PGA
BLKSH
CONV
T. G
29 BLKFB DC
OFFSET
SERIAL INTERFACE
17 18 19 20 45 44 43
CDS_CS
IC5202(TG/CDS)
4 15 16 6
40 39
21
H1
22
H2
29
V4
32
V3
28
V2 (TG/V_DRIVER)
30
V1
33
SUB
OSCIN 36
TO DSP
VD 32
VDVHS
35
SCLK
SERIAL- 34
PULSE SDATA
PARARELLE
GENERATOR
DECODER
LATCH 33
38
RESET
IC4201,IC4202
(F/Z/I/MDA)
HALL
AMP
MOTOR
DRIVE
AMP
REG 4.8V
IC4201
R4262
Q4251
+ 6
8
AMP
C4256
( WHITE )
BALANCE
SENSOR
C D
IC4001(DSP)
(DSP)
D9 AD9
11
D8 10 AD8
D7 AD7
9
100
D6 8 AD6
AD9 AD9
D5 7 AD5
OB
AD4
D4 6
CLAMP
D3 5 AD3
AD0 AD0
AD2 IH
D2 4 110
DL
D1 3 AD1
AD0
D0 2
IH
16 CDS_CLK 137
ADCLK
DL
AD1_CK
TG_CLK 118
CAMCK
132
CLKI
CAM_ADCK 138
CAMADCK
113
HDTG
114
VDTG
99
LHFO
112
ID
38
PBLK
134
CLKCPU
S03
SCK3
34
V_DSP_CS
79
V_PULSE
169
CLKOUT
145
35
CDS_CS AD0
SCK3 146
AD1
SO3 147
AD2
36 148
AD3
CCD_CS
21 149
DSGAT AD4
150
AD5
151
AD6
152
AD7
155
AD8
156
AD9
8 157
CK AD10
10 158
AD11
CLDCLK
159
47
AD12
AHD
48 160
VHD IC101(CPU) AD13
161
45
VGAT AD14
3 162
ID AD15
41
SEN
46
DSGAT
REG_3.2V 140
R/W(L) R/W_L
42
RST
142
ASTB ASTB
C5222 R5215
141
DSTB(L) DSTB_L
123
FOCUS_SENS
98
124 OMT OMT
ZOOM_SENS
170
WAIT(L) WAIT_L
73
V_FF
V_FF
LENS_CLK
26
LENS_MDA_CLK 110
VDVHS VDVHS
104
FRP CFM
10
SCK3
15
HD HD_H
9
SO3 96
VD_H
VD
LENS_CS 41
LENS_MDA_CS 103
FI
FI
4
DSP_RST
25 OSD_CLK
OSD_CLK
31 OSD_CS
OSD_CS
24 OSD_DATA
OSD_DATA
4 DSP_REST
DSP_RST
16
IRIS_O/C
125 71
HOLE X1
R4209,C4206
59 70
+ LPF IRIS_PWM X2
- +
3 TXD
TXD
(COMP)
RXD
94
RXD
2 RXD
RXD
12
IR_FLICK
121
IR_DC
E
4-55 4-56
V/H
APT
CTL
G
γ
PROCESS
CTL
Y/C
γ
SEPA WB
(3LINE)
RGB G
MATRIX
SEPA CTL
γ
126
STD
124 SDCK
DATA
SET
C Y
125 SLD
117
ADDV
116
HDMASK
7 BUS0
AD0
8
9 84 87 73 81 92 96 91
11
12
13
14
16
17
18
20
IC4002
21
22 (DSP)
6 3 14 7 18
23
24
25 BUS15
AD15
C Y
5 RW
R/W_L
6 ASTB
ASTB
1 DSTB
DSTB_L
35 OMT
OMT
36 BUSY
WAIT_L
WRITE BUFFER
129 SW30
V_FF
240 VREF0
VDVHS
31 FRP
CFM
WRITE RESISTOR
HDCPU
28
HD_H
VDCPU
29
VD_H
30 FLDCPU
FI
MEMORY CELL ARRAY
140
DSP_REST
CLR
X101 IC4003(DSP)
MAIN SYSTEM
CLOCK (16MHz)
193 BLK_1 11
BLK1
BLK1
194 BLK_2 13
BLK2 BLK2
195 VBLK 15
VBLK VBLK
192 VB 18
VB VB
191 VG 17
VG
VG
188 VR 16
VR VR
186 VC_1 12
VC1 VC1
187 VC_2
14
VC2 VC2
185 CLKOSD 8
CLKOSD OSCIN
F
C V_PB_C
a
DSP CONTROL
INTER FACE
C Y
67 72 59 66 88 97 90
95
17 16 15
34 37 26 33 25 22 24 23
C Y
(MEMORY)
DOUT BUFFER
READ RESISTOR
(OSD)
DSP_REST
4
PCL
3 OSD_DATA
DATA
2 OSD_CS
CS
1 OSD_CLK
CLK
G H