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9 Block Diagram
9.1.
Main Block Diagram
IFD_OUT1
IFD_OUT2
SIF_OUT
Video_OUT
D/A TUNER
IEC
ENGS9301D5F
Analog AV Input
Analog AV Input
OPT
HDMI1
HPD* < STM
HDMI_5V_DET
HDMI 5V DET* > STM
HDMI2
HPD* < STM
HDMI_5V_DET* > STM
S5/ S3.3/ S1.8
IF_AGC
Low-IF
DMD_IIC0
SCL
SDA
SIF_OUT
TS-OUT
Video_OUT (CVBS)
HS1BCLKIN
HSBCLKOUT
HS0BCLKIN
HS1SYNCIN
HSSYNCOUT
HS0SYNCIN
< FE_XRST
Reset
HS1VALIN
HSVALOUT
HS0VALIN
HS1DIN[0:7]
HSDOUT[0:7]
HS0DIN[0:7]
Cross Stream Switch
S9/S5
DVB-T
FEAIN
A-Chip VDD
DTV Decoder
PC
VIF Decoder
SIFIN
ADC
SIF Decoder
P-IIC
P IIC
Video Input
RGB /YPbPr /CVBS /YC
R1, G1, B1, V1
R
L
Pr
Pb
Y/V
HS,VS
AV-SW
V-SW
ADC
Analog Video
AV1 /
(Thru)
DAC
YUV1
R2A11023FT
(W/O EU)
LIN1_R, LIN1_L
Audio Input
Main Audio L/R
V
L
Side
A-SW
R
ADC
(Thru)
AV2
CVBS
DAC
A-Chip
SOUND_VCC
PWM0LP
PWM
PWM0LN
PWM0RP
AMP
PWM0RN
LV4923V
Optical OUT
IECOUT
Rx*
DDC* > STM, Peaks
STM
Rx*
HDMI
Rx
MUX
DDC* > STM, Peaks
x3
CPU BUS
CTRL
ADR
DATA
S5/ S3.3
STB5/5VS
XNMIRQ
XIRQ1
XECS1
XERE
XEAS
XEAS
XEWE0
XEWE0
ECLK
ESZ0
ESZ1
XEDK
XEWE1
BOOTSWAP
Support
ERXW
(XRST)
Card
EA[7:0],EA[24]
< TV_SOS
AMP/HP MUTE
MONITOROUT MUTE
ED[15:0]
< DTV_XRST
S3.3
2G - Function
ED[7:0]
NAND
VIErA-CAST Browser
Flash
EU MHP
S12
1G
UK BBC iPlayer
Latin GINGA MHP
Peaks
DCDC_EN
NAND-IF
DCDC
TS-IN
XNFCE,XNF
PCOE
CI-IF
DTV_XRST >
WP
PCWE
PCWAIT
NFCLE,NFAL
SW_OFF_DET >
PCIORD
PCCD1
E
PCIOWR
S1.2
S1.5
S1.8
S3.3
XNFWE,XNF
PCRESET
PCCD2
EA[15:1]
ED[15:0]
RE
PCCE1
PCREADY
NANDRYBY
Trans Port Decoder
CPUBUS
NAND-IF
IIC
DMD
DMD-IIC0
P-IIC2 (For DMD only)
DMD-IIC1
P
Peaks
k
Video
IPR INS
Format
Processor
Processor
sLD2
DSP
DDR
2G-1333Hz
S1.5
S1.5
FHD
D-Book6.x Network
MKV decording
DDR3+
DDR3+
x16
x32
1G
1G
1333Hz
I2S
SW
A-D Chip
Internal BUS
EEP
ASIA,Latin
ELSE: 16k
For STM
For Peaks
STB3.3
S3.3
AMP
PWM
EEP
EEPROM_WP
EEP
16k
P-IIC
SPDIF
STM
SW
EEP_WP >
D-Chip
STM
STM
IIC
STM IIC
STM-IIC
Serial
IIC
Serial
STM-Serial0
P-IIC0
P-Serial0
DMD IIC
STM-Serial1
P-IIC1
P-Serial1
XOR
DMD_IIC
(P-IIC2)
P-UART0
0
P-IIC3
P-UART2
DMD_IIC
1
STM-D Chip
CLK
Communication Register
GEN
STB3.3
STB1.2
24.576MHz
27
S9
S12/S5
(SD-Data-VCC)
S9 REG
S9-REG
Analog
3.3/1.8
ASIC
UHS-1
< (SDVOLC)
REG
AN34043A
STB3.3V/1.2V_REG
OVP
Safety
STB5V Reset IC (STM)
SOS
Circuit
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
< MON_MUTE
OCP/OVP/TV-SOS
< SP_HP_MUTE
HP_MUTE,EXT_MUTE
UHS-I_REG
PWM >
TV_SOS
PWM
Back Light
PWM >
BL_ON >
BL_SOS <
INVERTER
S3.3
or
S9
LED Driver
STB3.3
STB1.2
TEMP
SENSOR
INV-LED
P-IIC
For EEFL
XRST POWER_DET
STB_XRST
PWMA
PANEL_LED_ON >
LCD
Driver
(LPL),LPR,POLL,POLR
PANEL
Ctrl
CPV,GDATA1,GDATA2
LD
mini-LVDS 156MHz RGB24bit
7pair(6data+1clk 156M) Single
LCD
Driver
EEP
P-IIC
2k
LCD_EEP_WP >
S5
USB
USB*VBUS >
< USB*OC
USB
S5
Power SW
S5
USB Memory
S5
SD_PWR_ON >
< SD_COIN_DET
SD Reg
S3.3
ExFAT: yes
SD-Data-VCC
SDXC
High Speed: no
UHS-I : no
SDCLK,SDCMD,SDVOLC,
SDDAT[3:0],SDCD,SDWP
<
KEY3
POWER KEY
< KEY1
CONTROL PANEL KEY
TH-L50EM5S
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