Sony STR-DH540 Service Manual page 55

Pin No. Pin Name
98 RESET
99 TMS
100 VDD_INT
I/O
Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096
CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution
I
from the hardware reset vector address. The RESET input must be asserted (low) at power-
up.
I Test Mode Select (JTAG). Used to control the test state machine.
- Power supply terminal (+1.2V) (for core)
Description
STR-DH540
55