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15.17. DG-Board (1 of 4) and GH-Board Block Diagram
D1
D2
D2+
1
D2G
2
3
D2-
D1+
4
D1G
5
D1-
6
D0+
7
D0G
8
D0-
9
10
CLK+
11
CLKG
CLK-
12
CEC
13
N.C.
14
SCL
15
16
SDA
17
DDCG
+5V
18
HPDT
19
GH10
HDMI IN 3
MAIN 5V
MAIN2 3.3V
Q3801
GH11
16
11
10
DG11
15
20
21
MAIN 5V
MAIN2 3.3V
DG9
HDMI IN 1
1
D2+
2
D2G
3
D2-
4
D1+
5
D1G
6
D1-
7
D0+
8
D0G
9
D0-
10
CLK+
11
CLKG
12
CLK-
13
CEC
14
N.C.
15
SCL
16
DDC DATA
17
DDCG
18
+5V
19
HPDT
1
D2+
2
D2G
3
D2-
4
D1+
5
D1G
6
D1-
7
D0+
8
D0G
9
D0-
10
CLK+
11
CLKG
12
CLK-
13
CEC
14
N.C.
15
SCL
16
DDC DATA
17
DDCG
18
+5V
19
HPDT
DG8
HDMI IN 2
TH-65PV600A/M
DG-Board (1 of 4) and GH-Board Block Diagram
IC3801
HDMI EQ & SW
GH HDMI IN 3
10
BDT2P
ADT2P
40
9
BDT2N
ADT2N
39
7
BDT1P
ADT1P
34
TP3804
BDT1N
A
ADT1N
6
B
33
4
BDT0P
ADT0P
31
3
BDT0N
ADT0N
30
IC3802
46
BCKP
ACKP
28
EQUALIZER
45
BCKN
ACKN
27
DDC EEPORM(2kbit)
SEL
6
SCL
36
(H:A/L:B)
5
SDA
CE
25
IC3803
13
14
16
17
20
21
23
24
5V<->3.3V
TP3801
TP3802
8
VCC
VCC2
3
SCLIN
SCLOUT
6
SDAIN
SDAOUT
2
8
19
20
22
23
25
26
28
29
9
29
23
12
11
9
8
6
5
3
2
22
IC1901
DDC EEPROM
5
SDA
6
SCL
40
39
34
33
31
30
28
27
25
36
MAIN2 3.3V
ROX2+
10
BDT2P
YDT2P
13
52
ROX2-
9
BDT2N
YDT2N
14
51
A
ROX1+
7
BDT1P
YDT1P
16
48
ROX1-
EQUALIZER
6
BDT1N
YDT1N
17
47
B
ROX0+
4
BDT0P
YDT0P
20
44
ROX0-
3
BDT0N
YDT0N
21
43
IC1903
ROXC+
46
BCKP
YCKP
23
40
ROXC-
45
BCKN
HDMI EQ & SW
YCKN
24
39
IC4022
MAIN 1.8V
DDC EEPROM
MAIN5V
MAIN 3.3V
D4052
HDMI I/F RECEIVER
6
SCL
VCC
8
5
SDA
WC
7
Q4084
D4051
R1X2+
71
R1X2-
70
R1X1+
67
R1X1-
66
R1X0+
63
R1X0-
62
R1XC+
59
R1XC-
58
30
DSCL1
D2
S2
D1
S1
29 DSDA1
Q4071
Q4083
33
R1PWR5V
5V
3.3V
DG DIGITAL SIGNAL PROCESSOR
MICOM
HDMI INTERFACE
MAIN 5V
D3814
IC4014
MAIN 3.3V
AD 2.5V
D3813
VCC
8
Q3802
1
VDD
VOUT
5
Q3804
WC
7
TP3803
IC4027
MAIN3.3V
MAIN 1.8V
7
VIN
VOUT
1
MAIN2 3.3V
1
2
7
MAIN3.3V
Q1905
5
4
14
6
7
Q1906
26
27
17
25
24
TP1903
HDMI_WP
WC
7
Q1904
IC1909
VCC
8
MAIN5V
D1913
D1914
5V<->3.3V
8
VCC
3
SCLIN
6
SDAIN
R0PWR5V 34
DSCL0
32
TMDS DATA
DSDA0
31
RECEIVER
28
AND
CSCL
SCL1
TMDS DECODER
CSDA
27
SDA1
CLKINB2
ODCK
121
HSIB
HSYNC
2
VSIB
VSYNC
3
HDCP
AP_DE
1
CIPHER DECRYPTOR
DE
REFCH_HDMI
XTALIN
97
IC4026
142
141
YB0-YB9
132
VIDEO
123
IC4025
INTERFACE
136
AUDIO DAC
UB0-UB9
133
119
MCLK
Clock
1
TMDS DATA
Divider
RECEIVER
110
AND
H:MUTE
MUTE_OUT
SMUTE
TMDS DECODER
MUTE OUT
77
6
INTERFACE
MCLK
RX_MCLK
88
SCK
RX_SCK
BICK
86
2
AUDIO
AUDIO
RX_SD0
SDTI
SD0
INTERFACE
Data
84
3
HDCP
INTERFACE
WS
RX_WS
LRCK
CIPHER DECRYPTOR
85
4
HDMI_RST
RESET
102
HDMI_INT
INT
104
HDMI_WP
99
IC4029
MAIN3.3V
2.5V
DLL 2.5V
1
VDD
VOUT
5
IC4017
IC4040
AD 2.5V
MAIN 3.3V
PLL 2.5V
MAIN 3.3V
MAIN2.5V
PLL 2.5V
MAIN 2.5V
1
VDD
VOUT
5
1
VDD
VOUT 5
IC4030
IC4032
MAIN 5V
PLL 3.3V
MAIN1.8V
MAIN1.8V
MAIN1.2V
PLL 3.3V
MAIN 1.2V
1
VIN
VOUT
5
8
1
VIN
VOUT
5
CONT
IC1503
PLL2 3.3V
MAIN 5V
PLL2 3.3V
1
VIN
VOUT
5
6
1
IC1904
SWITCH
H:Aport=Front
5
3
2
7
L:Bport=Rear
IC1902
IIC SWITCH
MAIN2_3.3V
1
3
8
10
H:Aport=Front
L:Bport=Rear
VCC2
1
2
13
4
5
9
6
11
12
SCLOUT
2
SDAOUT
7
Q1907
INV.
MAIN5V
7
8
9
14
PDN
5
IC4028
MAIN9V
P
AUDIO AMP
5
R
AOUTR
7
10
6
Interpolator
Modulator
3
L
1
AOUTL
11
2
Interpolator
Modulator
MAIN5V
MAIN5V
HOTPLUG
CABLE IN;Hi/NORM
AUDIO MUTE
Hi;MUTE
Q1902
CABLE OUT;LOW/MUTE
AND 5V DET
Low;DETECT HPD5V
HOTPLUG
CABLE IN;Hi/NORM
AUDIO MUTE
Hi;MUTE
Q4068
CABLE OUT;LOW/MUTE
AND 5V DET
Low;DETECT HPD5V
TH-65PV600A/M
DG-Board (1 of 4) and GH-Board Block Diagram
TH-65PV600A / TH-65PV600M
1
R
2
L
3
4
HDMI_SEL
HDMI_DAC_PD
HPD1
Q1901
HDMI_5V_DET1
HPD2
Q4065
HDMI_5V_DET2
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