Page 1 User’s Manual M010 Motherboard...
Page 2 00RWKHUERDUG Information in this document is subject to change without notice and does not represent a commitment on the part of Creative Technology Ltd. No part of this manual may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose without the written permission of Creative Technology Ltd.
Page 3 Creative Labs FCC Part 15: This equipment has been tested and found to comply Model Number: M010 with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable has been tested according to the FCC / CISPR22/85 protection against harmful interference in a residential installation.
Page 4: Table Of Contents
&RQWHQWV ,QWURGXFWLRQ Document Conventions .................... viii 3URGXFW'HVFULSWLRQ Overview ..........................1-1 Feature Summary...................... 1-1 Creative M010 Board Layout................... 1-4 Online Support ........................1-5 Design Specifications......................1-6 Processor..........................1-12 System Memory........................1-13 ECC Memory......................1-15 DIMM Installation Guidelines................1-15 Intel® 820 Chipset......................1-17 USB .........................
Page 5 Diskette Drive Controller..................1-25 Keyboard and Mouse Interface................1-26 Power Management Features....................1-27 Software Support.....................1-27 Hardware Support ....................1-33 7HFKQLFDO5HIHUHQFH Introduction..........................2-1 Memory Map .........................2-1 I/O Map..........................2-2 DMA Channels........................2-7 PCI Configuration Space Map....................2-8 Interrupts ..........................2-9 PCI Interrupt Routing Map ....................2-11 Connectors ...........................2-13 Back Panel Connector.....................2-14 Midboard Connectors....................2-19 Front Panel Connectors...................2-36 Jummper Block .......................2-42...
Page 6 2YHUYLHZRI%,26)HDWXUHV Introduction ........................... 3-1 BIOS Flash Memory Organization ..................3-2 Resource Configuration......................3-3 PCI Autoconfiguration ..................... 3-3 System Management BIOS (SMBIOS)................3-4 BIOS Upgrades ........................3-5 Language Support..................... 3-5 Custom Splash Screen....................3-5 Recovering BIOS Data ......................3-6 Boot Options ......................... 3-6 CD-ROM and Network Boot...................
Page 7 Power Menu.........................4-28 Boot Menu ...........................4-29 IDE Drive Configuration Submenu..................4-31 Exit Menu..........................4-32 (UURU0HVVDJHVDQG%HHS&RGHV BIOS Error Messages......................5-1 Port 80h POST Codes ......................5-4 Bus Initialization Checkpoints....................5-15 Speaker..........................5-17 BIOS Beep Codes........................5-18 Enhanced Diagnostics ......................5-19...
Page 8 Introduction This manual provides you with information on how to set up and use your motherboard: Chapter 1, “Product Description” Provides an overview and design specifications of the motherboard, as well as chipset, memory and processor information. Chapter 2, “Technical Reference” Provides tabular data on System Memory Map, I/O Map, DMA Channels and PCI Configuration Space Map.
Page 9: Document Conventions
Document Conventions The following typographical conventions are used throughout this document: Table i: Document conventions This Represents bold Text that must be entered exactly as it appears. italic Title of a book or a placeholder, which represents the information you must provide.
Page 10: Overview
Product Description Overview Feature Summary Table 1-1 summarizes the Creative M010 board's major features. Table 1-1: Feature Summary Form Factor ATX (12.0 inches by 8.2 inches) Processor Support for Intel® Pentium® III and Pentium II processors Memory Two 168-pin SDRAM Dual Inline Memory Module (DIMM) sockets...
Page 11 Table 1-1: Feature Summary Video AGP universal connector supporting 1X, 2X, and 4X AGP cards Peripheral Two serial ports Interfaces Two Universal Serial Bus (USB) ports One parallel port Two IDE interfaces with Ultra DMA and ATA 66 support One diskette drive interface Expansion Six add-in card expansion slots: Capabilities...
Page 12 Table 1-1: Feature Summary Instantly Support for PCI Local Bus Specification Revision 2.2 Available PC Suspend to RAM support Wake on PS/2 keyboard and USB ports Wake on Support for system wake up using an add-in network interface card with LAN†...
Page 13: Creative M010 Board Layout
Creative M010 Board Figure 1-1 shows the location of the major components on the Creative M010 board. Layout Audio/Modem Riser (AMR) connector Back Panel Connectors AGP universal connector PCI bus add-in card connectors 242-contact slot connector Intel 82820 Memory Controller...
Page 14: Online Support
Online Support Find information about the Creative M010 board under "Product Info" or "Customer Support" at these World Wide Web sites: http://www.intel.com/design/motherbd http://support.intel.com/support/motherboards/desktop Find "Processor Data Sheets" or information about "Proper Date Access in Systems with Intel Motherboards" at these World Wide Web sites: http://www.intel.com/design/litcentr...
Page 15: Design Specifications
Design Specifications Table 1-2 lists the specifications applicable to the Creative M010 board. Table 1-2: Specifications Reference Specification Version, Revision Date, The information is available from... Name Title and Ownership AC’97 Audio Codec Version 2.1, May 1998, ftp://download.intel.com/ pc-supp/platform/ Intel Corporation...
Page 16 Table 1-2: Specifications Reference Specification Version, Revision Date, The information is available from... Name Title and Ownership Advanced Version 1.2, http://www.microsoft.com/hwdev/busbios/ Power February 1996, amp_12.htm Management Intel Corporation, BIOS Microsoft Corporation. Interface Specification ATA-3 Information Version 6, ATA Anonymous FTP Site: Technology - October 1995, ftp://www.dt.wdc.com/ata/ata-3/...
Page 17 Table 1-2: Specifications Reference Specification Version, Revision Date, The information is available from... Name Title and Ownership Enhanced Version 1.7, http://standards.ieee.org/reading/ieee/ Parallel Port 1997, std_public/description/busarch/1284.1- IEEE std Institute of Electrical and 1997_desc.html 1284.1-1997 Electronic Engineers. EI Torito Bootable CD- Version 1.0, the Phoenix Web site at: ROM format January 25, 1995,...
Page 18 Table 1-2: Specifications Reference Specification Version, Revision Date, The information is available from... Name Title and Ownership PCI Bus Version 1.1, http://www.pcisig.com/ Power December 18, 1998, Management PCI Special Interest Interface Group. Specification Plug and Plug and Play Version 1.0a, http://www.microsoft.com/hwdev/respec/ Play BIOS...
Page 19 Table 1-2: Specifications Reference Specification Version, Revision Date, The information is available from... Name Title and Ownership System SMBIOS Version 2.3, http://developer.intel.com/ial/wfm/design/ Management August 12, 1998, smbios BIOS Award Software International Inc., Dell Computer Corporation, Hewlett- Packard Company, Intel Corporation, International Business Machines Corporation, Phoenix Technologies...
Page 20 Table 1-2: Specifications Reference Specification Version, Revision Date, The information is available from... Name Title and Ownership Universal Version 1.1, http://www.usb.org/developers Serial Bus September 23, 1998, Specification Compaq Computer Corporation, Intel Corporation, Microsoft Corporation, and NEC. Wired for Version 2.0, http://developer.intel.com/ial/WfM/ Management December 18, 1998,...
Page 21: Processor
Processor The Creative M010 board supports a single Pentium III or Pentium II processor. The host bus speed is automatically selected. The processor must be secured by a retention mechanism attached to the Creative M010 board. The Creative M010 board supports a single 242-contact slot type processor as listed in Table 1-3.
Page 22: System Memory
System Memory The Creative M010 desktop board has two DIMM sockets supporting 168-pin SDRAM DIMMs. When installing memory in the Creative M010 desktop board, proper memory installation guidelines should be followed as described in DIMM Installation Guidelines The Creative M010 desktop board supports the following memory features:...
Page 23 Table 1-4: Supported DIMM Sizes and Configurations (non-ECC specified) DIMM Total Number of Non-ECC SDRAM SDRAM Size SDRAM DIMM Component Component Components on Organization* Density Organization DIMM* 32MB 4M x 64 64 Mbit 4M x 16 64 MB 8M x 64 64 Mbit 8M x 8 64 MB...
Page 24: Ecc Memory
ECC Memory The Creative M010 board supports both ECC and non-ECC DIMMs, however, ECC DIMMs will operate in non-ECC mode only. DIMM Installation The Creative M010 board requires supported DIMMs be installed under the guidelines listed below. Guidelines If you have one DIMM, install it in Bank 0 (the memory slot closest to the processor).
Page 25 Table 1-5 summarizes the DIMM installation guidelines given above. Table 1-5: Installation Guideline Summary Types of DIMMs to be Bank 0 Bank 1 installed... One DIMM DIMM (Empty) Two DIMMs - Same size, Either DIMM Either DIMM same number of sides (both single-or both double-sided) Two DIMMs - Different...
Page 26: Intel® 820 Chipset
Intel® 820 Chipset The Intel 820 chipset consists of the following devices: 82820 Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus 82801AA I/O Controller Hub (ICH) with AHA bus 82802AB Firmware Hub (FWH) 82805AA Memory Translator Hub (MTH) The chipset provides the host, memory, AGP, and I/O interfaces shown in Figure 1-2.
Page 27 )RULQIRUPDWLRQDERXW 5HIHUWR 7KH,QWHOFKLSVHW KWWSGHYHORSHULQWHOFRP 7KHUHVRXUFHXVHGE\WKHFKLSVHW &KDSWHU 7KHFKLSVHW©VFRPSOLDQFHZLWK$&3, ¦'HVLJQ6SHFLILFDWLRQV§RQSDJH $30$&© AGP is a high-performance interface for graphics-intensive applications, such as 3D applications. While based on the PCI Local Bus Specification, Rev. 2.1, AGP is independent of the PCI bus and is intended for exclusive use with graphical display devices. AGP overcomes certain limitations of the PCI bus related to handling large amount of graphics data with the following features: Pipelined memory read and write operations that hide memory access latency...
Page 28: Usb
The Creative M010 board has two USB ports onboard; one USB peripheral can be connected to each port. For more than two USB devices, an external hub can be connected to either port. The two USB ports are implemented with stacked back panel connectors. The Creative M010 board fully supports UHCI and uses UHCI-compatible software drivers.
Page 29: Ide Support
The drive reports the transfer rate and translation mode to the BIOS. The Creative M010 board supports laser servo (LS-120) diskette technology through its IDE interfaces. The LS-120 drive can be configured as a boot device by setting the BIOS Setup...
Page 30 SCSI Hard Drive Activity The SCSI hard drive activity LED connector is a 1 x 2-pin connector that allows add-in SCSI controller to use the same LED as the IDE controller. This connector can be connected to the LED Connector LED output of the add-in controller card.
Page 31 If the battery and AC power fail, standard defaults, not custom defaults, will be loaded into CMOS RAM at power-on. The recommended method of accessing the date in systems with Creative M010 boards is indirectly from the Real-Time Clock (RTC) via the BIOS. The BIOS on Creative M010 boards contains a century checking and maintenance feature.
Page 32: I/O Controller
I/O Controller The SMSC LPC47M102 I/O Controller provides the following features: Low pin count (LPC) interface 3.3V operation Two serial ports One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port (EPP) support Serial IRQ interface compatible with serialized IRQ support for PCI systems PS/2-style mouse and keyboard interfaces Interface for one 1.2 MB, 1.44 MB, or 2.88 MB diskette drive Intelligent power management, including a programmable wake up event interface...
Page 33: Serial Ports
Serial Ports The Creative M010 board has two 9-pin D-Sub serial port connectors located on the back panel. The serial ports' NS16C550-compatible UARTs support data transfers at speeds up to 115.2 kbits/sec with BIOS support. The serial ports can be assigned as COM1 (3F8h), COM2 (2F8h), COM3 (3E8h), or COM4 (2E8h).
Page 34: Parallel Port
Parallel Port The connector for the multimode bidirectional parallel port is a 25-pin D-Sub connector located on the back panel. In the BIOS Setup program, the parallel port can be configured for the following: Output only (PC AT†-compatible mode) Bi-directional (PS/2 compatible) )RULQIRUPDWLRQDERXW 5HIHUWR 7KHORFDWLRQRIWKHSDUDOOHOSRUWFRQQHFWRU...
Page 35: Keyboard And Mouse Interface
Keyboard and Mouse PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these connectors are protected with a PolySwitch† circuit that, like a self-healing fuse, reestablishes Interface the connection after an overcurrent condition is removed. The keyboard controller contains the AMI keyboard and mouse controller code, provides the keyboard and mouse control functions, and supports password protection for power-on/reset.
Page 36: Power Management Features
• Wake on PME# Software Support The software support for power management includes: ACPI If the Creative M010 board is used with an ACPI-aware operating system, the BIOS can provide ACPI support. Otherwise, it defaults to APM support. Product Description 1-27...
Page 37 From the operating system, such as the Standby menu item in Windows† 98 In standby mode, the Creative M010 board can reduce power consumption by spinning down hard drives, and reducing power to, or turning off of, VESA DPMS-compliant monitors.
Page 38 ACPI gives the operating system direct control over the power management and Plug and Play functions of a computer. The use of ACPI with the Creative M010 board requires an operating system that provides full ACPI support. ACPI features include:...
Page 39 The operating system uses information from applications and user settings to put the system as a whole into a low-power state. Table 1-7 lists the power states supported by the Creative M010 board along with the associated system power targets. See the ACPI specification for a complete description of the various system and power states.
Page 40 Table 1-7: Power States and Targeted System Power Global States Sleeping States Device States Targeted System States Power* G0 - working state S0 - working C0 - D0 - working state Full power > 60 W working G1 - Sleeping S1 - CPU stopped C1 - stop D1, D2, D3 - device...
Page 41 Plug and Play device enumeration and configuration. ACPI is used only to enumerate and configure Creative M010 board devices that do not have other hardware standards for enumeration and configuration. PCI devices on the Creative M010 board, for example, are not enumerated by ACPI.
Page 42: Hardware Support
Hardware Support The Creative M010 board provides several hardware features that support power management, including: Power connector Fan connectors If the Wake on LAN and Wake on LAN technology Instantly Available technology Instantly Available technology features are used, ensure that...
Page 43 When used with an ATX-compliant power supply that supports remote power-on/ -off, the Creative M010 board can turn off the system power through software control. To enable soft- off control in software, advanced power management must be enabled in the BIOS Setup program and in the operating system.
Page 44 Fan Connectors The Creative M010 board has three fan connectors. The functions of these connectors are described in Table 1-9 Table 1-9: Fan Connector Descriptions Connector Function System fan (Fan 1) Provides +12 V DC for a system or chassis fan. The fan voltage can be switched on or off, depending on the power management state of the computer.
Page 45 Technology Interface. Upon detecting a Magic Packet† frame, the LAN subsystem asserts a wakeup signal that powers up the computer. Depending on the LAN implementation, the Creative M010 board supports Wake on LAN technology in one of two ways: Through the Wake on LAN technology connector (APM or ACPI S5 only)
Page 46 7KHVLJQDOQDPHVRIWKH:DNHRQ5LQJFRQQHFWRU 7DEOHRQSDJH Instantly Available Instantly Available technology enables the Creative M010 board to enter the ACPI S3 (Suspend-to-RAM) sleep-state. While in the S3 sleep-state, the computer will appear to be off Technology (the power supply is off, the fans are off, and the front panel LED is amber if dual-color, or off if single-color.) When signaled by a wake-up device or event, the system quickly returns to its...
Page 47 Figure 1-4: Location of Standby Power Indicator LED 1-38 Product Description...
Page 48 • Second call enables access (when the appropriate software is loaded) Detects incoming calls differently for external as opposed to internal modems: • For external modems, the Creative M010 board hardware monitors the Ring-Indicate (RI) input of serial port A (serial port B does not support this feature) •...
Page 49 Wake from USB USB bus activity wakes the computer from an ACPI S1 or S3 state. Wake from PS/2 Keyboard PS/2 keyboard activity wakes the computer from an ACPI S1 or S3 state. Wake from USB requires the use of a USB peripheral that supports Wake from USB.
Page 50: Introduction
Technical Reference Introduction Chapter 2 contains several standalone tables. Table 2-1 describes the System Memory Map, Table 2-2 shows the I/O Map, Table 2-3 lists the DMA Channels, Table 2-4 defines the PCI Configuration Space Map, and Table 2-5 describes the Interrupts. The remaining sections in this chapter are introduced by text found with their respective section headings.
Page 51: I/O Map
Table 2-1: System Memory Map Address Range Address Range Size Description (decimal) (hex) 640 K - 800 K A0000 - C7FFF 160 KB Video memory and BIOS 639 K - 640 K 9FC00 - 9FFFF 1 KB Extended BIOS data (movable by memory manager software) 512 K - 639 K 80000 - 9FBFF...
Page 52 Table 2-2: I/O Map Address (hex) Size Description 0072 - 0073 2 bytes System CMOS 0080 - 008F 16 bytes DMA controller 0092 1 byte Fast A20 and PIC 00A0 - 00A1 2 bytes 00B2 - 00B3 2 bytes APM control 00C0 - 00DF 32 bytes 00F0...
Page 53 Table 2-2: I/O Map Address (hex) Size Description 0228 - 022F* 8 bytes LPT3 0278 - 027F* 8 bytes LPT2 02E8 - 02EF* 8 bytes COM4/Video (8514A) 02F8 - 02FF* 8 bytes COM2 One of these 8 bytes MPU-401 (MIDI) ranges : 0320 - 0327 0330 - 0337...
Page 54 FFA8 - FFAF 8 bytes Secondary master IDE registers 96 contiguous bytes starting on a 128- ICH (ACPI + TCO) byte divisible boundary 64 contiguous bytes starting on a 64- Creative M010 board resource byte divisible boundary Technical Reference 2-5...
Page 55 Table 2-2: I/O Map Address (hex) Size Description 64 contiguous bytes starting on a 64- Onboard audio controller byte divisible boundary 32 contiguous bytes starting on a 32- ICH (USB) byte divisible boundary 16 contiguous bytes starting on a 16- ICH (SMBus) byte divisible boundary 4096 contiguous bytes starting on a...
Page 56: Dma Channels
DMA Channels Table 2-3: DMA Channels DMA Channel Data Width System Resource Number 8- or 16-bits Audio 8- or 16-bits Audio/parallel port 8- or 16-bits Diskette drive 8- or 16-bits Parallel port (for ECP or EPP)/Audio 8- or 16-bits DMA controller 16-bits Open 16-bits...
Page 57: Pci Configuration Space Map
PCI Configuration Space Map Table 2-4: PCI Configuration Space Map Device Function Description Number Number Number (hex) (hex) (hex) Memory controller of Intel 82820 component AGP connector Link to PCI bridge PCI-to-LPC bridge IDE controller USB controller #1 SMBus controller Reserved AC '97 audio controller (optional) AC '97 modem controller (optional)
Page 58 Table 2-4: PCI Configuration Space Map Device Function Description Number Number Number (hex) (hex) (hex) PCI slot 2 PCI slot 3 PCI slot 4 PCI slot 5 Interrupts Table 2-5: Interrupts System Resource I/O channel check Reserved, intervel timer Reserved keyboard buffer full Reserved, cascade interrupt from slave PIC COM2* COM1*...
Page 59 Table 2-5: Interrupts System Resource Diskette drive LPT1* Real-time clock Reserved for ICH system management bus User available User available On board mouse port (if present, else user available) Reserved, math coprocessor Primary IDE (if present, else user availabe) Secondary IDE (if present, else user availabe) * Default, but can be changed to another IRQ 2-10 Technical Reference...
Page 60: Pci Interrupt Routing Map
PCI Audio and the ICH USB Controller, the add-in card now shares interrupts with these onboard interrupt sources. Table 2-6 lists the PIRQ signals used in the M010 board and shows how the signals are connected to the PCI bus connectors and to the onboard PCI interrupt sources.
Page 61 Table 2-6: PCI Interrupt Routing Map ICH PIRQ Signal Name PCI Interrupt Source PIRQA PIRQB PIRQC PIRQD AGP Connector INTA INTB ICH Audio Controller ICH Modem Controller ICH USB Controller PCI Audio PCI Bus Connector 1 (J4E1) INTA INTB INTC INTD PCI Bus Connector 2 (J4D1) INTD...
Page 62: Connectors
Connectors This section describes the Creative M010 board's connectors. The connectors can be divided into three groups, as shown in Figure 2-1 Back panel connectors Only the back panel connectors (see page 2-14) of the Creative M010 board have overcurrent protection. The...
Page 63: Back Panel Connector
Back Panel Connector Figure 2-2 shows the location of the back panel connectors. The back panel connectors are color-coded in compliance with PC 99 recommendations. The figure legend below lists the colors used. USB port 0 Parallel port PS/2 mouse port PS/2 keyboard port USB port 1 Serial port A...
Page 64 ,WHP 'HVFULSWLRQ &RORU )RUPRUH ,WHP 'HVFULSWLRQ &RORU )RUPRUH LQIRUPDWLRQVHH LQIRUPDWLRQVHH 36PRXVHSRUW *UHHQ 7DEOH 3DUDOOHOSRUW %XUJXQG\ 7DEOH 36NH\ERDUGSRUW 3XUSOH 7DEOH 6HULDOSRUW$ 7HDO 7DEOH & 86%SRUW %ODFN 7DEOH 6HULDOSRUW% 7HDO 7DEOH 86%SRUW %ODFN 7DEOH Table 2-7: PS/2 Keyboard/Mouse Connectors Signal Name Data Not connected Ground Fused +5 V...
Page 65 Table 2-8: USB Connectors Signal Name +5 V (fused) USBP0#[USBP1#] USBP0[USBP1] Ground Signal names in brackets ([ ]) are for USB port 1. Table 2-9: Parallel Port Connector Standard Signal Name ECP Signal Name EPP Signal Name STROBE# STROBE# WRITE# 2-16 Technical Reference...
Page 66 Table 2-9: Parallel Port Connector Standard Signal Name ECP Signal Name EPP Signal Name ACK# ACK# INTR BUSY BUSY#, PERIHACK WAIT# PERROE PE, ACKREVERSE# SELECT SELECT SELECT AUDOFD# AUDOFD#, HOSTACK DATASTB# FAULT# FAULT#, PERIPHREQST FAULT# INIT# INIT#, REVERSERQST# FAULT# SLCTIN# SLCTIN# ADDRSTB# 18 - 25...
Page 67 Table 2-11: MIDI/Game Port Connector Signal Name Signal Name +5 V (fused) +5 V (fused) JOY4 JOY6 JOYTIME0 JOYTIME2 Ground MIDI-OUT Ground JOYTIME3 JOYTIME1 JOY7 JOY5 MIDI-IN +5 V (fused) 2-18 Technical Reference...
Page 68: Midboard Connectors
Midboard Connectors The midboard connectors are divided into the following functional groups: Peripheral interfaces and indicators (see page 2-20) • SCSI LED • Secondary IDE • Primary IDE • Diskette drive Hardware control (see page 2-24) • Power supply fan control (Fan 2) •...
Page 69 Peripheral Interfaces and Figure 2-3 shows the location of the peripheral interface and indicator connectors. Indicators Figure 2-3: Peripheral Interface and Indicator Connectors 2-20 Technical Reference...
Page 70 ,WHP 'HVFULSWLRQ 5HIHUHQFH'HVLJQDWRU 6&6,/('VHH7DEOH -% 6HFRQGDU\,'(VHH7DEOH -* & 3ULPDU\,'(VHH7DEOH -* 'LVNHWWHGULYHVHH7DEOH -* Table 2-12: SCSI LED Connector (J7B3) Signal Name SCSI activity Not connected Table 2-13: PCI IDE Connectors (J7G1, Primary and J6G1, Secondary) Signal Name Signal Name Reset IDE Ground Data 7 Data 8...
Page 71 Table 2-13: PCI IDE Connectors (J7G1, Primary and J6G1, Secondary) Signal Name Signal Name Data 3 Data 12 Data 2 Data 13 Data 1 Data 14 Data 0 Data 15 Ground DDRQ0 [DDRQ1] Ground I/O Write# Ground I/O Read# Ground IOCHRDY P_ALE (Cable Select pull-up) DDACK0# [DDACK1#]...
Page 72 Table 2-14: Diskette Drive Connector (J8G1) Signal Name Signal Name Ground DENSEL Ground Reserved FDEDIN Ground FDINDX# (Index) Ground FDM00# (Motor Enable A) Ground No connect Ground FDDS0# (Drive Select A) Ground No connect No connect FDDIR# (Stepper Motor Direction) Ground FDSTEP# (Step Pulse) Ground...
Page 73 Hardware Control and Figure 2-4 shows the location of the hardware control and power connectors Power Figure 2-4: Hardware Control and Power Connectors 2-24 Technical Reference...
Page 74 ,WHP 'HVFULSWLRQ 5HIHUHQFH 'HVLJQDWRU 3RZHUVXSSO\IDQFRQWURO)DQVHH7DEOH -/ 3URFHVVRUIDQ)DQVHH7DEOH -0 & 0DLQSRZHUVHH7DEOH -0 6\VWHPIDQ)DQVHH7DEOH -( :DNHRQ/$1WHFKQRORJ\VHH7DEOH -& &KDVVLVLQWUXVLRQVHH7DEOH -& :DNHRQ5LQJVHH7DEOH -% )RULQIRUPDWLRQDERXW 5HIHUWR 7KHSRZHUFRQQHFWRU ¦3RZHU&RQQHFWRU§RQSDJH 7KHIXQFWLRQVRIWKHIDQFRQQHFWRUV ¦)DQ&RQQHFWRUV§RQSDJH :DNHRQ/$1WHFKQRORJ\ ¦:DNHRQ/$17HFKQRORJ\§RQSDJH :DNHRQ5LQJWHFKQRORJ\ ¦:DNHRQ5LQJ§RQSDJH Technical Reference 2-25...
Page 75 Table 2-15: Power Supply Fan 2 Control Conncetor (J5L1) Signal Name Ground +12 V FAN2_TACH Table 2-16: Processor Fan 3 Connector (J2M1) Signal Name Ground +12 Volts FAN3_CPU_HDR_GND_R Table 2-17: Main Power Connector (J6M2) Signal Name Signal Name +3.3 V +3.3 V +3.3 V -12 V...
Page 76 Table 2-17: Main Power Connector (J6M2) Signal Name Signal Name +5 V Ground Ground Ground PWRGD (Power Good) TP_PWRCONN_18 +5 V (Standby) +5 V +12 V +5 V Table 2-18: System Fan 1 Connector (J8D1) Signal Name Ground +12 V FAN1-TACH Table 2-19: Wake on LAN TEchnology Connector (J7C2) Signal Name...
Page 77 Table 2-20: Chassis Intrustion Connector (J7C1) Signal Name INTRUDER# Ground Table 2-21: Wake on Ring Connector (J7B2) Signal Name Ground RINGA# 2-28 Technical Reference...
Page 78 All of the PCI bus connectors are bus master capable. PCI bus connector 2 has SMBus signals routed to it. This enables PCI bus add-in boards with SMBus support to access sensor data on the Creative M010 board. The specific SMBus signals are as follows: •...
Page 79 ,WHP 'HVFULSWLRQ 5HIHUHQFH'HVLJQDWRU 3&,EXVFRQQHFWRUVHH7DEOH -$ 3&,EXVFRQQHFWRUVHH7DEOH -% & 3&,EXVFRQQHFWRUVHH7DEOH -& 3&,EXVFRQQHFWRUVHH7DEOH -' 3&,EXVFRQQHFWRUVHH7DEOH -( $*3XQLYHUVDOFRQQHFWRUVHH7DEOH -( Table 2-22: PCI Bus Connectors (J4A1, JaB1,J4D1, J4E1) Signal Name Signal Name Signal Name Signal Name Ground (TRST#) -12 V AD16 AD17 +12 V Gound (TCK)* +3.3 V C/BE2#...
Page 80 Table 2-22: PCI Bus Connectors (J4A1, JaB1,J4D1, J4E1) Signal Name Signal Name Signal Name Signal Name +5 V INTD# +3.3 V LOCK# Reserved no connect Reserved** PERR# (PRSNT1#)* +5 V (I/O) Reserved Reserved*** +3.3 V Reserved no connect Ground SERR# (PRSNT2#)* Ground Ground...
Page 81 Table 2-22: PCI Bus Connectors (J4A1, JaB1,J4D1, J4E1) Signal Name Signal Name Signal Name Signal Name AD26 AD27 AD06 +3.3 V Ground AD25 AD04 AD05 AD24 +3.3 V Ground AD03 IDSEL C/BE3# AD02 Ground +3.3 V AD23 AD00 AD01 AD22 Ground +5 V (I/O) +5 V (I/O)
Page 82 Table 2-23: AGP Interface Connector (J5E1) Signal Name Signal Name Signal Name Signal Name +12V No connect Vcc3.3 Vcc3.3 TYPEDET# AD22 AD21 Reserved AD20 AD19 No Connect No Connect Ground Ground Ground Ground AD18 AD17 INTA# INTB# AD16 C/BE2# RST# Vcc3.3 Vcc3.3 GNT1#...
Page 83 Table 2-23: AGP Interface Connector (J5E1) Signal Name Signal Name Signal Name Signal Name SBA3 SBA2 SERR# SBSTB# SB_STB AD15 C/BE1# Ground Ground Vcc3.3 Vcc3.3 SBA5 SBA4 AD13 AD14 SBA7 SBA6 AD11 AD12 Ground Ground AD10 +3.3 V aux C/BE0# Vcc3.3 Vcc3.3 AD30...
Page 84: Front Panel Connectors
Front Panel Figure 2-6 shows the location of the front panel connectors. Connectors Figure 2-6: Front Panel Connectors Technical Reference 2-35...
Page 85 ,WHP 3LQV 'HVFULSWLRQ )URQWSDQHO&RQQHFWRU DQG ,QIUDUHGSRUW 7DEOHRQSDJH DQG 5HVHWVZLWFK & DQG +DUGGULYHDFWLYLW\/(' DQG 3RZHU6OHHS0HVVDJH ZDLWLQJ/(' DQG 3RZHUVZLWFK DQG 1RFRQQHFW $X[LOLDU\)URQW3DQHO3RZHU DQG $X[LOLDU\3RZHU/(' /('&RQQHFWRUVHH7DEOH FRQQHFWRU3LQNH\HG RQSDJH 2-36 Technical Reference...
Page 86 Table 2-24: Front Panel Connector (J8G2) Signal In/Out Description Signal In/Out Description HD_PWR Hard disk LED HDR_BLNK_GRN Front panel green pull-up (330 HDA# Hard disk active HDR_BLNK_YEL Front panel yellow LED Ground FPBUT_IN Power switch FP_RESET# Reset switch Ground +5 V IR Power IRRX IrDA serial input...
Page 87 Reset Switch Connector Pins 5 and 7 can be connected to a momentary SPST type switch that is normally open. When the switch is closed, the Creative M010 board resets and runs the POST Hard Drive Activity LED Pins 1 and 3 can be connected to an LED to provide a visual indicator that data is being read from or written to a hard drive.
Page 88 SW_ON# pin to ground for at least 50 ms to signal the power supply to switch on or off. (The time requirement is due to internal debounce circuitry on the Creative M010 board.) At least two seconds must pass before the power supply will recognize another on/off signal.
Page 89 Jumper Block The Creative M010 board has one jumper block. Figure 2-7 shows the location of the Creative M010 board's jumper block. Do not move any jumper with the power on. Always turn off the power and unplug the power cord from the computer before changing a jumper setting.
Page 90 When the Creative M010 board jumper is set to configuration mode and the computer is powered-up, the BIOS compares the CPU version and the microcode version in the BIOS and reports if the two match.
Page 91: Mechanical Considerations
Considerations Form Factor The Creative M010 board is designed to fit into an ATX-form-factor chassis. Figure 2-8 illustrates the mechanical form factor for the Creative M010 board. Dimensions are given in inches. The outer dimensions are 8.20 inches by 12.00 inches. Location of the I/O connectors and mounting holes are in compliance with the ATX specification (see “Design Specifications”...
Page 92: I/O Shield
I/O Shield The back panel I/O shield for the Creative M010 board must meet specific dimension and material requirements. Systems based on this CreativeM010 board need the back panel I/O shield to pass certification testing. Figure 2-9 show the critical dimensions of the chassis- dependent I/O shield for Creative M010 boards with and without audio.
Page 93: Electrical Considerations
Electrical Considerations Power Consumption Table 2-29 lists voltage and current measurements for a computer that contains the Creative M010 board and the following: 533 MHz Intel Pentium III processor with a 512 KB cache 128 MB SDRAM 3.5-inch diskette drive 1.6 GB IDE hard disk drive...
Page 94: Add-In Board Consideration
$ $&3,6 Add-in Board The Creative M010 board is designed to provide 2 A (average) of +5 V current for each add-in board. The total +5 V current draw for add-in boards in a fully-loaded Creative M010 board Consideration (all seven expansion slots filled) must not exceed 14 A.
Page 95 Standby Current Power supplies used with the Creative M010 desktop board must be able to provide enough standby current to support the Instantly Available (ACPI S3 sleep state) configuration as Requirements outlined in below. Values are determined by specifications such as PCI 2.2. Actual measured values may vary.
Page 96 6WDQGE\&XUUHQW ,QVWDQWO\$YDLODEOH&XUUHQW 'HVFULSWLRQ 5HTXLUHPHQWV 6XSSRUW(VWLPDWHGIRU P$ LQWHJUDWHGERDUGFRPSRQHQWV ,QVWDQWO\$YDLODEOH6WDQGE\ 363RUWV &XUUHQW6XSSRUW 3&,VORWVZDNH • Estimated for add-on HQDEOHG Components 3&,VORWVQRQZDNH • Add to Instantly Available HQDEOHG total current requirement 6HHLQVWUXFWLRQVDERYH :2/KHDGHU $05 86%3RUWV PD[LPXPIRU ERWKSRUWV * Dependent upon system configuration IBM PS/2 Port Specification (Sept 1991) states: 275 mA for keyboard 70 mA for the mouse (not wake-enable device) Technical Reference 2-47...
Page 97: Fan Power Requirements
One wake-enabled device @ 500 mA USB hub @ 100 mA Three USB non wake-enabled devices connected @ 2.5 mA each Fan Power The Creative M010 Desktop Board is capable of supplying 174 mA per fan connector (maximum). Requirements Both USB ports are capable of providing up to 500 mA during normal G0/S0 operation.
Page 98: Power Supply Considerations
Creative M010 board. Considerations Measurements account only for current sourced by the Creative M010 board while running in idle modes of the started operating systems. Additional power required will depend on configurations chosen by the integrator.
Page 99 2-50 Technical Reference...
Page 100: Introduction
Overview of BIOS Features Introduction The Creative M010 board uses an Intel/AMI BIOS, which is stored in flash memory and can be upgraded using a disk-based program. In addition to the BIOS, the flash memory contains the BIOS Setup program, POST, APM, the PCI auto-configuration utility, and Plug and Play support.
Page 101: Bios Flash Memory Organization
BIOS Flash The Intel 82802AB Firmware Hub (FWH) includes a 4 Mbit (512 KB) symmetrical flash memory device. Internally, the device is grouped into eight 64-KB blocks that are individually Memory erasable, lockable, and unlockable. Figure 3-1 shows the organization of the flash memory. Organization The last two 8 KB blocks of the fault tolerance area are the parameter blocks.
Page 102: Resource Configuration
Resource Configuration PCI Autoconfiguration The BIOS can automatically configure PCI devices. PCI devices may be onboard or add-in cards. Autoconfiguration lets a user insert or remove PCI cards without having to configure the system. When a user turns on the system after adding a PCI card, the BIOS automatically configures interrupts, the I/O space, and other system resources.
Page 103: System Management Bios (Smbios)
PCI IDE Support If you select Auto in the BIOS Setup program, the BIOS automatically sets up the two PCI IDE connectors with independent I/O channel support. The IDE interface supports hard drives up to Ultra ATA/66 and recognizes any ATAPI devices, including CD-ROM drives, tape drives, and Ultra DMA drives (see “Design Specifications”...
Page 104: Bios Upgrades
Using this support, an SMBIOS service-level application running on a non- Plug and Play operating system can obtain the SMBIOS information. For information about Refer to The Creative M010 board's compliance level with SMBIOS “Design Specifications” on page 1-6 BIOS Upgrades A new version of the BIOS can be upgraded from a diskette using the Intel®...
Page 105: Language Support
For information about Refer to The Intel World Wide Web site “Online Support” on page 1-5 Language Support The BIOS Setup program and help messages can be supported in 32 languages. Five languages are available in the BIOS: US English, German, Italian, French, and Spanish. The default language is US English that is present unless another language is selected in the BIOS Setup program.
Page 106: Boot Options
To create a BIOS recovery diskette, a bootable diskette must be created and the BIOS update files copied to it. BIOS upgrades and the Intel Flash Memory Upgrade utility are available from Intel Customer Support through the Intel World Wide Web site. For information about Refer to The BIOS recovery mode jumper settings...
Page 107: Usb Legacy Support
USB Legacy USB legacy support enables USB devices such as keyboards, mice, and hubs to be used even when no operating system USB drivers are in place. USB legacy support is used in accessing Support the BIOS Setup program and installing an operating system that supports USB. By default, USB legacy support is set to Auto.
Page 108: Bios Security Features
BIOS Security The BIOS includes security features that restrict access to the BIOS Setup program and who can boot the computer. A supervisor password and a user password can be set for the BIOS Setup Features program and for booting the computer, with the following restrictions: The supervisor password gives unrestricted access to view and change all the Setup options in the BIOS Setup program.
Page 109 Table 3-1: Supervisor and User Password Functions Password Password Password Supervisor User Mode Setup Options to Enter During Mode Setup Boot Supervisor Can change Can change Supervisor Supervisor None only all options a limited Password number of options User only Can change Enter Password User...
Page 110: Introduction
BIOS Setup Program Introduction The BIOS Setup program can be used to view and change the BIOS settings for the computer. The BIOS Setup program is accessed by pressing the <F2> key after the Power-On Self-Test (POST) memory test begins and before the operating system boot begins. The menu bar is shown below.
Page 111 Table 4-2 lists the function keys available for menu screens. Table 4-2: BIOS Setup Program Function Keys BIOS Setup Program Description In this chapter, all examples of Function Key the BIOS Setup Program menu bar include the maintenance <*> or <*> Selects a different menu screen (Moves the cursor left or right) menu;...
Page 112: Maintenance Menu
Maintenance Menu Maintenance Main Advanced Security Power Boot Exit Extended Configuration The menu shown in Table 4-3 is for clearing Setup passwords and enabling extended configuration mode. Setup only displays this menu in configuration mode. See “Jumper Block” in chapter 2 for configuration mode setting information. Table 4-3: Maintenance Menu Feature Options...
Page 113: Extended Configuration Submenu
Extended Configuration Maintenance Main Advanced Security Power Boot Exit Extended Configuration Submenu The submenu represented by Table 4-4 is for setting video memory cache mode. This submenu becomes available when User Defined is selected under Extended Configuration. Table 4-4: Extended Configuration Submenu Feature Options Description...
Page 114: Main Menu
Main Menu Main Maintenance Advanced Security Power Boot Exit Table 4-5 describes the Main Menu. This menu reports processor and memory information and is for configuring the system date and system time. Table 4-5: Main Menu Feature Options Description BIOS Version No options Displays the version of the BIOS.
Page 115: Advanced Menu
Advanced Menu Maintenance Main Advanced Security Power Boot Exit PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration Table 4-6 Describes the Advanced Menu. This menu is used for setting advanced features that are available through the chipset. Table 4-6: Advanced Menu Feature Options...
Page 116 Table 4-6: Advanced Menu Feature Options Description Boot Settings No options Configures Plug and Play and the Configuration Numlock key, and resets configuration data. When selected, displays the Boot Configuration submenu. Peripheral Configuration No options Configures peripheral ports and devices. When selected, displays the Peripheral Configuration submenu.
Page 117: Pci Configuration Submenu
PCI Configuration Submenu Maintenance Main Advanced Security Power Boot Exit PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented by Table 4-7 is for configuring the IRQ priority of PCI slots individually.
Page 118 Table 4-7: PCI Configuration Submenu Feature Options Description PCI Slot 3 IRQ Priority • Auto (default) Allows selection of IRQ priority. IRQ Priority selections for PCI slots 3 and 5 are linked. Selections made to PCI Slot 3 IRQ Priority are repeated in PCI Slot 5 IRQ Priority.
Page 119: Boot Configuration Submenu
Boot Configuration Submenu Advanced Maintenance Main Security Power Boot Exit PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented by Table 4-8 is for setting Plug and Play options, resetting configuration data, and the power-on state of the Numlock key. Table 4-8: Boot Configuration Submenu Feature Options...
Page 120: Peripheral Configuration Submenu
Table 4-8: Boot Configuration Submenu Feature Options Description Reset Config Data • No (default) No does not clear the PCI/PnP configuration data • Yes stored in flash memory on the next boot. Yes clears the PCI/PnP configuration data stored in flash memory on the next boot.
Page 121 The submenu represented in Table 4-9 is used for configuring computer peripherals. Table 4-9: Peripheral Configuration Submenu Feature Options Description Serial port A • Disabled Configures serial port A. (Note: If Plug and Play • Enabled Auto assigns the first free COM port, OS is enabled in the Boot •...
Page 122 Table 4-9: Peripheral Configuration Submenu Feature Options Description Serial port B • Disabled Configures serial port B. Auto assigns the first free COM port, • Enabled • Auto (default) normally COM2, the address 2F8h, and the interrupt IRQ3. An * (asterisk) displayed next to an address indicates a conflict with another device.
Page 123 Table 4-9: Peripheral Configuration Submenu Feature Options Description Parellel port • Disabled Configures the pareller port. Auto assigns LPT1 the address 378h • Enabled • Auto (default) and the interrpt IRQ7. An * (asterisk) displayed next to an address indicates a conflict with another device.
Page 124 Table 4-9: Peripheral Configuration Submenu Feature Options Description Interrupt • IRQ 5 Specifies the interrupt for the • IRQ7 (default) (Visible only if enabled is parallel port. selected in parallel port) DMA Channel • 1 Specifies the DMA channel. (Visible only if ECP •...
Page 125: Ide Configuration Submenu
IDE Configuration Maintenance Main Advanced Security Power Boot Exit Submenu PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The menu represented in Table 4-10 is used to configure IDE device options Table 4-10: IDE Configuration Submenu Feature Options Description...
Page 126 Table 4-10: IDE Configuration Submenu Feature Options Description Primary IDE No options Reports type of connected IDE device. When selected, displays the Primary IDE Master Master submenu. Primary IDE No options Reports type of connected IDE device. When selected, displays the Primary IDE Slave submenu. Slave Secondary No options...
Page 127: Ide Configuration Sub-Submenus
IDE Configuration Maintenance Main Advanced Security Power Boot Exit Sub-submenus PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Primary IDE Master Primary IDE Slave Secondary IDE Master Secondary IDE Slave Diskette Configuration Event Log Configuration Video Configuration The sub-submenus represented in Table 4-11 are used to configure IDE devices IDE Configuration Sub-Submenus Table 4-11: Feature...
Page 128 Table 4-11: IDE Configuration Sub-Submenus Feature Options Description Type • None Specifies the IDE configuration mode for IDE • User devices. • Auto (default) User allows capabilities to be changed. • CD-ROM Auto fills-in capabilities from ATA/ATAPI • ATAPI Removable device.
Page 129 Table 4-11: IDE Configuration Sub-Submenus Feature Options Description Transfer Mode • Standard Specifies the method for moving data to/from • Fast PIO 1 (default) the drive. • Fast PIO 2 • Fast PIO 3 • Fast PIO 4 • FPIO 3 / DMA 1 •...
Page 130: Diskette Configuration Submenu
Diskette Configuration Advanced Maintenance Main Security Power Boot Exit PCI Configuration Submenu Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented by Table 4-12 is used for configuring the diskette drive. Table 4-12: Diskette Configuration Submenu Feature Options Description...
Page 131: Event Log Configuration Submenu
Event Log Configuration Maintenance Main Advanced Security Power Boot Exit PCI Configuration Submenu Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented by Table 4-13 is used to configure the event logging features Table 4-13: Event Log Configuration Submenu Feature Options...
Page 132: Video Configuration Submenu
Video Configuration Submenu Maintenance Main Advanced Security Power Boot Exit PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented inTable 4-14 is for configuring the video features. Table 4-14: Video Configuration Submenu Feature Options Description...
Page 133: Security Menu
Security Menu Maintenance Main Advanced Security Power Boot Exit The menu represented by Table 4-15 is for setting passwords and security features. Table 4-15: Security Menu If no password entered previously: Feature Options Description User Password Is No options Reports if there is a user password set.
Page 134 Table 4-15: Security Menu User Access • Limited Specifies user's access Level • No access privileges. (Supervisor only) • View Only • Full (default) Unattended Start • Enabled Enables or disables wake on • Disabled (default) LAN technology feature. Locks keyboard.
Page 135: Power Menu
Power Menu Maintenance Main Advanced Security Power Boot Exit The menu represented in Table 4-16 is for setting the power management features. Table 4-16: Power Menu Feature Options Description Power Management • Disabled Enables or disables the BIOS power • Enabled (default) management feature.
Page 136: Boot Menu
Boot Menu Maintenance Main Advanced Security Power Boot Exit IDE Drive Configuration The menu represented in Table 4-17 is used to set the boot features and the boot sequence. Table 4-17: Boot Menu Feature Options Description Quiet Boot • Disabled Disabled displays normal POST messages.
Page 137 Table 4-17: Boot Menu Feature Options Description On Modem • Stay-Off In APM mode only, specifies how the computer (default) Ring responds to an incoming call on an installed modem • Power-On when the power is off. 1st Boot Device •...
Page 138: Ide Drive Configuration Submenu
IDE Drive Configuration Maintenance Main Advanced Security Power Boot Exit IDE Drive Submenu Configuration The submenu represented in Table 4-18 is used to set the order in which the IDE drives boot. Changing the boot-order of a given drive causes the boot-order for the other drives to change automatically to accommodate your selection.
Page 139: Exit Menu
Exit Menu Maintenance Main Advanced Security Power Boot Exit The menu represented in Table 4-19 is for exiting the BIOS Setup program, saving changes, and loading and saving defaults. Table 4-19: Exit Menu Feature Description Exit Saving Changes Exits and saves the changes in CMOS SRAM. Exit Discarding Changes Exits without saving any changes made in the BIOS Setup program.
Page 140: Bios Error Messages
Error Messages and Beep Codes BIOS Error Table 5-1 lists the error messages and provides a brief description of each. Table 5-1: BIOS Error Messages Messages Error Message Explanation GA20 Error An error occurred with Gate A20 when switching to protected mode during the memory test.
Page 141 Table 5-1: BIOS Error Messages Error Message Explanation Cache Memory Bad An error occurred when testing L2 cache. Cache memory may be bad. CMOS Battery Low The battery may be losing power. Replace the battery soon. CMOS Display Type Wrong The display type is different than what has been stored in CMOS.
Page 142 Table 5-1: BIOS Error Messages Error Message Explanation Updated Failed NVRAM was invalid but was unable to be updated. Keyboard Error Error in the keyboard connection. Make sure keyboard is connected properly. KB/Interface Error Keyboard interface test failed. Memory Size Decreased Memory size has decreased since the last boot.
Page 143: Port 80H Post Codes
Table 5-1: BIOS Error Messages Error Message Explanation NVRAM / CMOS / NVRAM, CMOS, and passwords have been cleared. PASSWORD cleared by Jumper The system should be powered down and the jumper removed. <CTRL_N> Pressed CMOS is ignored and NVRAM is cleared. User must enter Setup.
Page 144 Table 5-2: Uncompressed INIT Code Checkpoints Code Description of POST Operation NMI is Disabled. Onboard KBC, RTC enabled (if present). Init code Checksum verification starting. Keyboard controller BAT test, CPU ID saved, and going to 4 GB flat mode. Do necessary chipset initialization, start memory refresh, and do memory sizing.
Page 145 Table 5-3: Boot Block Recovery Code Checkpoints Code Description of POST Operation Onboard Floppy Controller (if any) is initialized. Compressed recovery code is uncompressed in F000:0000 in Shadow RAM and give control to recovery code in F000 Shadow RAM. Initialize interrupt vector tables, initialize system timer, initialize DMA controller and interrupt controller.
Page 146 Table 5-4: Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation NMI is Disabled. To check soft reset/power-on. BIOS stack set. Going to disable cache if any. POST code to be uncompressed. CPU init and CPU data area init to be done. CMOS checksum calculation to be done next.
Page 147 Table 5-4: Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation Memory Refresh line is toggling. Going to check 15 µs ON/OFF time. To read 8042 input port and disable Megakey GreenPC feature. Make BIOS code segment writeable. To do any setup before Int vector init.
Page 148 Table 5-4: Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation Alternate Display memory R/W test passed. To look for the alternate display retrace checking. Video display checking over. Display mode to be set next. Display mode set. Going to display the power-on message. Different buses init (input, IPL, general devices) to start if present.
Page 149 Table 5-4: Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation Pattern to be tested written in extended memory. Going to write patterns in base 640k memory. Patterns written in base memory. Going to find out amount of memory below 1M memory.
Page 150 Table 5-4: Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation Memory size display adjusted due to relocation/ shadow. Memory test above 1M to follow. Memory testing/initialization above 1M complete. Going to save memory size information. Memory size information is saved. CPU registers are saved. Going to enter in real mode.
Page 151 Table 5-4: Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation Keyboard test started. Clearing output buffer, checking for stuck key, to issue keyboard reset command. Keyboard reset error/stuck key found. To issue keyboard controller interface test command. Keyboard controller interface test over.
Page 152 Table 5-4: Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation Setup options programming after CMOS setup about to start. Going for hard disk controller reset. Hard disk controller reset done. Floppy setup to be done next. Floppy setup complete.
Page 153 Table 5-4: Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation Coprocessor initialized. Going to do any initialization after Coprocessor test. Initialization after Coprocessor test is complete. Going to check extended keyboard, keyboard ID and num-lock. Going to display any soft errors. Soft error display complete.
Page 154: Bus Initialization Checkpoints
Table 5-4: Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation Uncompress SMBIOS module and init SMBIOS code and form the runtime SMBIOS image in shadow. Going to copy any code to specific area. Copying of code to specific area done. Going to give control to INT-19 boot loader.
Page 155 While control is inside the different bus routines, additional checkpoints are output to port 80h as WORD to identify the routines under execution. In these WORD checkpoints, the low byte of the checkpoint is the system BIOS checkpoint from which the control is passed to the different bus routines.
Page 156: Speaker
ISA PnP devices PCI devices Ω Speaker A 47 inductive speaker is mounted on the Creative M010 board. The speaker provides audible error code (beep code) information during POST. For information about Refer to The location of the onboard speaker...
Page 157: Bios Beep Codes
BIOS Beep Codes Whenever a recoverable error occurs during POST, the BIOS displays an error message describing the problem (see Table 5-8). The BIOS also issues a beep code (one long tone followed by two short tones) during POST if the video configuration fails (a faulty video card or no card installed) or if an external ROM module does not properly checksum to zero.
Page 158: Enhanced Diagnostics
Enhanced The enhanced diagnostics feature consists of a hardware decoder and four LEDs located between the audio connectors and the serial port B connector on the back panel. This feature Diagnostics requires no modifications to the chassis (other than I/O back panel shield) or cabling. Figure 5-1 shows the location of the diagnostic LEDs.
Page 159 Table 5-9: Diagnostic LED Codes Display BIOS Operation Display BIOS Operation Amber Power on, starting BIOS Green Undefined Amber Amber Amber Amber Amber Amber Amber Recovery mode Green Undefined Amber Amber Amber Amber Green Green Amber Processor, cache, etc. Green Undefined Amber Amber...
Page 160 Table 5-9: Diagnostic LED Codes Display BIOS Operation Display BIOS Operation Amber Video Green Undefined Green Green Amber Amber Green Green Amber IDE bus initialization Green Reserved Green Green Green Green Amber Amber Amber USB initialization Green Booting operating Green Green system Green...
Page 161 5-22 Error Messages and Beep Codes...
Page 162 Creative Labs, Inc. 1901 McCarthy Boulevard Milpitas CA 95035 Creative Technology Ltd 31, International Business Park Creative Resource Singapore 609921 Printed in Singapore...

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