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CMOS Setup Utility-Copyright (C) 1984-2000 Award Software
CPU Host/PCI Clock
System BIOS Cacheable
Video RAM Cacheable
Memory Hole At 15M-16M
AGP Aperture Size (MB)
AGP ISA Aliasing
AGP Secondary Lat Timer
AGP Fast Write
AGP Data Transfer Mode
SDRAM ECC Setting
Super Bypass Mode
SDRAM Timing setting by
x SDRAM PH Limit
x SDRAM Idle Limit
x SDRAM Trc Timing Value
x SDRAM Trp Timing Value
x SDRAM Tras Timing Value
x SDRAM CAS Latency
x SDRAM Trcd Timing Value
:Move Enter : Select +/-/PU/PD:Value F10:Save ESC: Exit F1:General Help
F5:Previous Values
Advanced Chipset Features
Default
Disabled
Disabled
Menu Level
Disabled
128
Changing the default
Enabled
setting may cause the
20h
system break down. If
Enabled
it did happen, you
4x
must power off then on
Disabled
, and press <Ins>
Enabled
immediately to change
Auto
system to safe mode.
8 Cycle
The board contains
8 Cycle
HP370 High performance
7 Cycle
PCI-to-IDE ATA-100
3 Cycle
ATAPI controller.
5 Cycle
2 Cycle
2 Cycle
F6:Fail-Safe Defaults
Item Help
F7: Optimized Defaults
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