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Chapter 1
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Auto Configuration
AT Bus Clock
DRAM Write WS
Page Mode Read WS
RAS Precharge Period
RAS-To-CAS Delay Time
EDO Read WS
DRAM Speculative Read
SDRAM CAS Latency
SDRAM Access Timing
SDRAM Speculative Read
Pipelined Function
DRAM Refresh Period
DRAM Data Integrity Mode
Memory Hole At 15M-16M
Primary Frame Buffer
*VGA Frame Buffer
Data Merge
Byte Merge
Fast Back-to-Bcak
: Enabled
Passive Release
: CLK 2/4
ISA Line Buffer
: X-2-2-2
Delay Transaction
: X-3-3-3
: 3T
: 3T
: X-2-2-2
: Disabled
: 3
: 3-4-7
: Disabled
: Enabled
: 30 us
: Disabled
: Disabled
: 2 MB
ESC : Quit
: Enabled
F1
: Enabled
F5
: Old Values
: Disabled F7
: Load Setup Defaults
: Disabled
Enabled
System Board
: Select Item
: Help
PU/PD/+/- : Modify
<Shift> F2 : Color
: Enabled
: Enabled
: Disabled
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