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5. System Diagrams
5.5. Connection Diagram4
Main board
5-5
CN 24
SA TA P OWER (2.0m m )
(48 On ly)
5V
1
DGND
2
CN 23
S ATA S IGNAL (48 On ly)
DGND
1
S ATA_TX_P
2
S ATA_TX_N
3
DGND
4
S ATA_RX_N
5
S ATA_RX_P
6
DGND
7
DGND
8
DGND
9
CN 2
UBS DEVICE
VBUS _C4_DEVICE
1
DN_C4_DEVICE
2
DP _C4_DEVICE
3
DGND
4
FGND
5
FGND
6
CN 5
REAR US B HOS T I/F(FDI)
VBUS _REAR_HOS T
1
DN_REAR_HOS T
2
DP _REAR_HOS T
3
DGND
4
FGND
5
FGND
6
CN 27
J TAG
3.3V
1
TDO
2
n TRS T
3
TCK
4
TMS
5
TDI
6
n RES ET
7
DGND
8
CN 16
GIGABIT ETHERNET(RJ -45)
DGND
1
1.8V
2
MDIP 3
3
MDIN3
4
MDIP 2
5
MDIN2
6
MDIP 1
7
MDIN1
8
MDIP 0
9
MDIN0
10
3.3V
11
LED1
12
3.3V
13
LED0
14
FGND
15
FGND
16
CN 21
DEBUGGER
3.3V
1
DEBUG_TXD
2
DEBUG_RXD
3
DGND
4
CN 31
J ACK DC-P OWER
5V
1
(N.C)
2
DGND
3
DGND
4
CN 19
CS T & ELEV MOT (1.5m m )
CS T_OP EN
1
P _S IZE3
2
P _S IZE2
3
DGND
4
P _S IZE1
5
(NC)
6
ELEV_S W_ON(24V)
7
EN_ELEV_MOT
8
CN 12
BLDC (1.5m m )
BLDC_DEVE_DIR
1
BLDC_DEVE_CLK
2
n BLDC_DEVE_READY
3
BLDC_DEVE_EN
4
BLDC_DEVE_GAIN
5
BLDC_DEVE_BRAKE
6
DGND
7
DGND
8
24VS 1
9
24VS 1
10
BLDC_MAIN_DIR
11
BLDC_MAIN_CLK
12
n BLDC_MAIN_READY
13
BLDC_MAIN_EN
14
5VP
15
BLDC_MAIN_BRAKE
16
DGND
17
DGND
18
24VS 1
19
24VS 1
20
P ARALLEL OP TION
P AP ER S IZE MODULE
(NEW, Ha rrie r) J C34-00001A
1
Ela va tin g DC m o to r
MT
2
CCW
10
CW/CCW
9
CLK
BLDC
8
READY
7
S S
BLDC
6
+5V
DEVE
5
BRAKE
MT
4
P GND
3
P GND
2
+24V
1
+24V
10
CW/CCW
9
CLK
BLDC
8
READY
7
S S
BLDC
6
+5V
MAIN
5
BRAKE
MT
4
P GND
3
P GND
2
+24V
1
+24V
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