Sony MHC-V77DW Service Manual page 95

BENTEN-MOTHERBOARD BOARD (1/11) IC6002 MT6323L (POWER MANAGEMENT)
Pin No. Pin Name
A1 SYSRSTB
A2 SRCLKEN
A3 XIN
A4 XOUT
A5 DVDD18_IO
A6 AUD_MISO
A8 DVDD18_DIG
A10 FSOURCE
A11 CHG_DM
A12 CHG_DP
A13 VCDT
A14 VBAT_VPA_A14
A15 VPA_A15
B1 AUXADC_AUXIN_GPS
B2 AVSS28_AUXADC
B3 GND_LDO_B3
B6 SIM2_AP_SCLK
B7 SPI_CSN
B8 AUD_MOSI
B9 SPI_MISO
B10 SPI_CLK
B11 ISINK3
B13 VPA_FB
B14 VBAT_VPA_B14
B15 VPA_B15
C1 AVDD33_RTC
C2 AUXADC_VREF18
C5 RTC_32K2V8
C7 INT
C8 SIM1_AP_SCLK
C9 AUD_CLK
C10 ISINK0
C11 ISINK1
C13 VPROC_FB
C15 VPROC_C15
D2 AVDD28_AUXADC
D3 AU_VIN0_P
D4 AU_VIN0_N
D5 GND_LDO_D5
D6 RTC_32K1V8
D7 SIM2_AP_SRST
D8 SIM1_AP_SRST
D9 SPI_MOSI
D11 ISINK2
D13 GND_VPROC_FB
D15 VPROC_D15
E1 AU_VIN2_N
E2 AU_VIN2_P
E6 GND_LDO_E6
E9 GND_LDO_E9
E11 GND_ISINK
E13 GND_VPROC_E13
I/O
I Watchdog reset from AP
I Enables 26MHz CLK
1. One of 32K crystal connection port while using crystal to generate 32kHz clock
I
2. Tie to ground with 32kHz crystal absence
1. One of 32K crystal connection port while using crystal to generate 32kHz clock
I
2. External 32kHz clocks input with 32kHz crystal absence
- Power of VIO18 IO/CORE
O Uplink AUDIO ADC serial data
- Power of VDlG18
- EFUSE power source
I USB D- for BC1.1 standard
I USB D+ for BC1.1 standard
I Fractional charger input voltage for charger detection
- Battery power supply input of VPA
O SW node of VPA
I AUXADC input
- GND for AUXADC
- Ground for LDO
I AP/PMIC SIM2 clock
I SPI interface's chip select signal to identify which device is selected
I Downlink DAC serial data
I/O SPI interface's serial data signal.Default: Output only.
I SPI interface's clock
O Current sink channel 3 output
I Feedback of VPA
- Battery power supply input of VPA
O SW node of VPA
- RTC LDO output. Supply of RTC macro where backup battery can be added.
O 1.8V AUXADC reference output
O RTC domain 32kHz clock output
Default: Output 0
O
Interrupt to BB, high active
I AP/PMIC SIM1 clock
I 26M clock (can be hopping)
O Current sink channel 0 output
O Current sink channel 1 output
I Feedback of VPROC
O SW node of VPROC
- 2.8V power input for AUXADC
I Analog input 1 positive
I Analog input 1 negative
- Ground for LDO
O VIO18 domain 32kHz clock output
I AP/PMIC SIM2 SRST
I AP/PMIC SIM1 SRST
SPI interface's serial data signal.
I/O
Default: lnput only.
O Current sink channel 2 output
I Remote sense on ground of VPROC
O SW node of VPROC
I Analog input 3 negative
Analog input 3 positive
I
- Ground for LDO
- Ground for LDO
- GND for ISINK
- Ground of VPROC
Description
MHC-V77DW
95