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Summary of Contents for Eurotech CPU-1450
- Page 1 An0065 CPU-1450: Soft Power Management Rev. 1.0 Feb 2006...
- Page 2 Eurotech assumes no responsibility for any inaccuracies that may be contained in this document. Eurotech makes no commitment to update or keep current the information contained in this manual. Eurotech reserves the right to make improvements to this document and/or product at any time and without notice.
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Page 3: Conventions
The following table lists conventions used throughout this guide. Warnings and Important Notices: Warning: Information to alert you to potential damage to a program, system or device or potential personal injury Information note: Indicates important features or instructions to observe An0065. CPU-1450 Soft Power Management... - Page 4 (This page is intentionally left blank.)
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Page 5: Table Of Contents
Table of Contents ............................5 Chapter 1 The Soft Power Management....................7 Chapter 2 CPU-1450 SPM block diagram architecture ................9 Intel 82801 ICH2 and System Power States..................11 System Power Planes ........................... 12 Power Management interface signals ....................12 Event Input Signals and Their Usage.................... - Page 6 (This page is intentionally left blank.)
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Page 7: Chapter 1 The Soft Power Management
(therefore decreasing power consumption) while keeping the capacity to restart work as soon as something happens. When the CPU-1450 module is powered off with SPM, just a little part of the board remains supplied. This part monitors the system inputs, looking for wake-up events. - Page 8 (This page is intentionally left blank.)
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Page 9: Chapter 2 Cpu-1450 Spm Block Diagram Architecture
APM-based legacy power management for non-ACPI implementations. In conclusion the complete CPU-1450 assembly is only APM-based legacy power management compliant. The core of the CPU-1450 soft power management is based on the Intel 82801 ICH2 chipset. - Page 10 A good point of start, to better understand the Power Management capabilities, is to refer directly to the chipset datasheet; consider that the CPU-1450 architecture is developed with the support for APM-based legacy power management for non ACPI implementations, it is not possible to refer exactly to the previous chipsets data sheets without considering some restrictions based on the hardware choices made.
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Page 11: Intel 82801 Ich2 And System Power States
Intel 82801 ICH2 and System Power States Table 1 shows the power states defined for ICH2-based platforms, the state names generally match the corresponding ACPI states, the hardware implementation of the CPU-1450 assembly does not support the greyed areas listed in the following table:... -
Page 12: System Power Planes
When SLP_S3# goes active (low), power is shut off to any circuit not required to wake the system. Since the ACPI standard S3 state requires that the memory context be preserved, power should be retained to the main memory. However the CPU-1450 does not support the MAIN SLP_S3# signal Suspend-to-Ram, so the main memory is shutdown together with the main plane. -
Page 13: Event Input Signals And Their Usage
CPU-1450 SPM block diagram architecture Event Input Signals and Their Usage Transitions rules for ICH2: Present State Transition Trigger Next State Processor halt instruction G0/S0/C1 Level 2 Read G0/S0/C2 Level 3 Read G0/S0/C3 G0/S0/C0 SLP_EN bit set G1/Sx or G2/S5state... - Page 14 (This page is intentionally left blank.)
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Page 15: Chapter 3 Cpu-1450 Power Management Connections
Chapter 3 CPU-1450 Power management connections To access the Soft Power Management capabilities of the CPU-1450, specific connections need to be made; this chapter is intended to document the connections versus the wake-up devices and to supply the CPU- 1450 in a Power Management compliant mode. -
Page 16: Ethernet
CPU-1450 Power management connections Ethernet The CPU-1450 J12 connector is used for the Ethernet connection during the Wake on LAN events. Ethernet Figure 3. J12Connector Layout Table 5. J12 Connector pin out Pin # Signal +3.3VSB ACTIVITY LED LINK LED The Eurotech Ethernet Transceiver To establish an Ethernet connection an Ethernet Transceiver must be used. -
Page 17: Serial 1 & Serial 2
Serial 1 & Serial 2 The CPU-1450 J8 connector is used for the Parallel, Serial 1 and Serial 2 ports. In the soft power management the Ring Indicator signal on the Serial sections can be used as a wake-up event. -
Page 18: Auxiliary Power Connector
CPU-1450 Power management connections Auxiliary Power Connector The CPU-1450 connector J9 is a 12-Pin (6x2) 2.54mm pitch connector and is used to power the module as an alternative to the PC/104-Plus bus, this connector also carries signals for power management... -
Page 19: Electrical Connections
CPU-1450 Power management connections Electrical connections In general if you want to supply the CPU-1450 with an ATX power supply here the connections you've to realize: J9 Aux PWR Signal Description Wire Colour Ground Black VDD (+5VDC) +5V DC signal N.C. -
Page 20: Development Kit Connections
PWRBTN# Figure 6. DTK Power Saving Connections In this application note we assume that you are using a development system where a CPU-1450 is installed with the connections described on Figure 6. Warning: Handle the module with care, considering that the board remains supplied even when it is not operating. -
Page 21: Chapter 4 Spm Management
Chapter 4 SPM Management The Soft Power Management capabilities of the CPU-1450 are integrated in the ICH2 82801 and the Super I/O PC87364. The CPU has the capability to be placed in a low-power operating mode where CPU activity is stopped and power consumption reduced. -
Page 22: Entering Low Power Mode
This chapter describes how to enter the low-power mode and the events that allow the user to wake-up the CPU-1450 from the sleep state. To minimize power consumption the CPU has to be placed into a low power consumption mode, this may be done via software. -
Page 23: Wake-Up Events
SPM Management Wake-up events The hardware of the CPU-1450 has been developed to allow the user to manage the Soft Power Management modes with the following wake-up event sources: Serial Port Ring Indicator pin Ethernet External Power Button Wake on RTC All the possible wake-up events can be enabled or disabled by setting the Soft Power Enable Registers. -
Page 24: External Power Button Pwrbtn
A hardware wake-up event from the sleeping state can be made at a predetermined time with an RTC alarm. In this case please be careful that the RTC is upgraded (Eurotech BIOS provides a user friendly interface to update the time and date), users have to initialise the RTC alarm registers and place the CPU into Low power consumption mode, when RTC reach RTC alarm count the CPU is waked up. -
Page 25: Chapter 5 Soft Power Management Registers
Chapter 5 Soft Power Management Registers The SPM register model consists of a number of fixed register blocks that perform designated functions. A register block consists of a number of registers that perform Status, Enable and Control Functions. Status bits are only set through some defined hardware events. Unless otherwise noted, Status bits are cleared by writing a HIGH to that bit position, and upon VTR POR. -
Page 26: Intel® 82801Ba I/O Controller Hub 2 (Ich2)
General Purpose Event 0 Enables Register. Used to enable wake events as Ring Indicator and PME. Table 9. Interesting ICH2 registers For a more detailed description please refer to Intel® 82801BA I/O Controller Hub 2 (ICH2) datasheet. An0065. CPU-1450 Soft Power Management... -
Page 27: Pm1_Sts Power Management 1 Status Register
SCI or SMI# (depending on the SCI_EN). 0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location. Table 10. PM1_STS Power Management 1 Status Register An0065. CPU-1450 Soft Power Management... -
Page 28: Pm1_En-Power Management 1 Enable Register
Timer Overflow Interrupt Enable (TMROF_EN)—R/W. Works in conjunction with the SCI_EN bit as described below: TMROF_EN SCI_EN Effect when TMROF_STS is set 0 x No SMI# or SCI 1 0 SMI# 1 1 SCI Table 11. PM1_EN—Power Management 1 Enable Register An0065. CPU-1450 Soft Power Management... -
Page 29: Pm1_Cnt-Power Management 1 Control Register
CPUSLP# to put processor in sleep state: Typically, maps to S1 state. ICH2-M (82801BAM): Reserved. 010 = ICH2 (82801BA): Reserved ICH2-M (82801BAM): Assert SLP_S1#: Typically, maps to S1 state. Table 12. PM1_CNT—Power Management 1 Control Register An0065. CPU-1450 Soft Power Management... -
Page 30: Gpe0_En-General Purpose Event 0 Enables Register
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the THRM_STS bit and generate a power management event (SCI or SMI). Table 13. GPE0_EN—General Purpose Event 0 Enables Register An0065. CPU-1450 Soft Power Management... -
Page 31: Superio National Pc87364
BADDR pin. The following table shows the selected base addresses as a function of BADDR. Index Data BADDR Register Register Table 14. BADDR Strapping Options For a more detailed description please refer to National / Winbond PC87364 128-Pin LPC Super I/O datasheet. An0065. CPU-1450 Soft Power Management... -
Page 32: Super I/O Configuration D Register (Siocfd)
0: No action (default at V power-up reset) 1: Inactivate PSON in Legacy mode Power Button Mode. This is a R/W bit. 0: Legacy (default at V power-up reset) 1: ACPI Table 15. Super I/O Configuration D Register (SIOCFD) An0065. CPU-1450 Soft Power Management... -
Page 33: Chapter 6 Software Examples
We are going to analyse some examples that may be useful understanding the following Wake-up events: Wake On RTC Serial Port Ring Indicator pin Wake On LAN (Ethernet) These software examples are also contained in the “An0065_SW_Package” available in the download area www.eurotech.it (“Tools” section of the CPU-1450). -
Page 34: Wake On Rtc Alarm
/* Eurotech SpA /* Version 0.5, date 07-02-2006 */ void main() printf( "Eurotech S.p.a. CPU-1450 Wake On RTC\n" ); printf( "Put to sleep a Cpu1450 and wake with RTC alarm to 2 minutes \n" ); printf( "\npress any key to continue\n");... - Page 35 Register D Day of Week 0Eh–7Fh 114 Bytes of User RAM Day of Month Table 16. RTC (Standard) RAM Bank The I/O locations 70h and 71h are the standard ISA location for the real-time clock. An0065. CPU-1450 Soft Power Management...
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Page 36: Wake On Ring Indicator Pulse
/* Eurotech SpA /* version 0.5 , date 07-02-2006 */ void main() printf( "Eurotech S.p.a. CPU-1450 Wake On Serial Ring\n" ); printf( "Put to sleep a Cpu1450 with pme and ring enabled\n" ); printf( "\npress any key to continue\n"); getch();... -
Page 37: Wake On Lan (Ethernet)
1. Verify that the Network peripheral is enabled in the BIOS. 2. Detect the MAC address of your CPU-1450 Ethernet adapter, this may be done using the DIAGS SW utility available from Intel or using the “An0065_SW_Package” available in the download area @ www.eurotech.it... - Page 38 MAC address of the CPU ; the program send a magic packet stream on the Ethernet cable compliant to the AMD magic packet specification. If you don’t have the ether-wake utility please refer to the bibliography. An0065. CPU-1450 Soft Power Management...
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Page 39: Cpu Power Consumption
Warning: Once the auxiliary power is on, the board is always supplied so take care to handle it. Without an ATX-like power supply the CPU-1450 Module could not work with SPM and the Power keeps all the board on. - Page 40 (This page is intentionally left blank.)
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Page 41: Chapter 8 Appendix
Chapter 8 Appendix... - Page 42 (This page is intentionally left blank.)
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Page 43: Related Software
Related Software Some software examples are contained in the “An0065_SW_Package” available in the download area @ www.eurotech.it (“Tools” section of the CPU-1450). Related Documents For more information please refer to the CPU-1450 user manual. http://www.eurotech.it Super I/O PC87364 www.national.com ICH2 82801 www.intel.com...
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