Theory Of Operation; Performance Test - Novatech 425A Instruction Manual

(Leading byte: 01=prescaler on)
2100: internal control registers
15: software revision as x.y, (1.5)
5.0

Theory of Operation

5.1 Please refer to the simplified System Block Dia-
gram in Figure 2 for the following discussion.
5.2 At every cycle of the 425A master clock, the 48-
bit Direct Digital Synthesizer (DDS) integrated cir-
cuit increments the phase of an internal accumulator
by a value determined by the frequency setting
loaded into the on-chip registers. This digital phase
value is converted on-chip to a sinusoidal amplitude
level and delivered to an on-chip 14-bit digital-to-
analog converter. The analog signal from this con-
verter is filtered by a 7th-order elliptical low pass
reconstruction filter, amplified and sent to the SINE
output connector.
5.3 The amplified Sine signal is diverted to a high-
speed zero crossing detector to generate the LVDS
output signal. The output of the detector is fed back
into the DDS IC to supply the clock for the internal
programmable divider.
5.4 The frequency generated by the DDS IC is
determined by the binary 48-bit frequency word
loaded into the frequency register on the 425A. The
output frequency is given by:
F = F
out binary
Where: F = 28,147,497.6710656 Hz (int.)
clock
F = Binary value in DDS IC.
binary
(F ranges from 0 to 2
binary
This reduces to:
F = F
out
for the internal (default) clock settings. The binary
setting is the customer's input setting scaled by a
factor of three and converted to a binary value with
the LSB having a weight of 10 Hz.
5.5 Since the DDS IC is a sampled data system, the
output frequency is limited to a maximum of 1/2 the
system clock frequency (F
NOVATECH INSTRUMENTS
48
*(100/3)*F /2 Hz
clock
47
-1)
*3.3333Hz
binary
47
<=2 -1). While it is
binary
possible to generate an output near 50% of the clock,
the distortion may be unacceptable. Therefore, the
output is limited to approximately 40% (approxi-
mately 350 MHz) of the system clock and a 7th-
order elliptical output filter is implemented on
board.
6.0

PERFORMANCE TEST

6.1 Install the 425A as directed in Section 3. Con-
nect your host controller and operate the 425A per
Section 4. The test limits assume a stable environ-
o
ment of 18-28 C.
Allow the 425A to warm up for at least 15 minutes
before performing any measurements. For best
results, the 425A should be verified in an
environment similar to its application.
6.2 See Table 2 for a list of recommended test
equipment to perform the following measurements.
Table 2: Recommended Test Equipment
Item
Oscilloscope
Frequency
Counter
Counter Time
Base
External Clock
6.3 Verify Frequency Accuracy. To verify the fre-
quency of the 425A, set the output sequentially to
each value in Table 3, with the clock source set to
internal ("C i"). Connect the recommended fre-
quency counter set to 50  termination and 0.1 Hz
resolution. Verify the limits show in Table 3. If you
do not use an external frequency standard for the
frequency counter, be sure to add the error of your
7
NOTE:
Minimum
Specification Recommended
500MHz, 50 Tektronix
TDS3052C
350MHz HP53132A
10MHz, Novatech
< 0.1ppm Instruments
±
Model 1450B
250-1000 Customer
MHz supplied
Rev 1.01, 425A Manual