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1.0
DESCRIPTION
1.1 The Model 425A is a 48-bit Direct Digital Syn-
thesized (DDS) Signal Generator in a small shielded
table top case with an asynchronous serial control
port (RS232). The 425A provides sine wave, LVDS
and LVCMOS output signals, which can be set from
250 kHz to 350 MHz in steps of 10 Hz per LSB
when using the internal VCTCXO clock
1.2 Relative phase is adjustable over the same inter-
face with 14-bits of resolution. Amplitude can be
fine trimmed over a 10-bit range from approxi-
mately 0.14 to 0.50 V
1.3 The LVCMOS output is optimized for frequen-
cies up to 125 MHz and, when used with its pro-
grammable divider, provides square wave clock
signals down to lower than 2 Hz.
1.4 The 425A can also be used with an External
Clock or Reference input. The external source can
either be a 10.0 MHz reference, which is phase-
locked internally, or a direct input of 250 to 1000
MHz. When used with the same external clock
source, multiple 425A remain phase synchronous.
2.0
SPECIFICATIONS
2.1 OUTPUTS
TYPES: Sine, LVDS and LVCMOS simultaneously.
IMPEDANCE: 50 (100 differential for LVDS)
RANGE: 250 kHz to 350 MHz with 10 Hz resolu-
tion (internal clock).
SINE AMPLITUDE: full scale approximately +7 dBm
(0.50 Vrms) into 50 load. Settable from 0.14 to
0.50 V
by the "V0" command. (14-bit DAC). ±3dB
rms
referenced to amplitude at 100 MHz.
2.2 LVCMOS AMPLITUDE
V
<0.5 V, V
>2.0 V into a series-terminated
OL
OH
load.
T
<2.5 ns. Duty Factor: 40-60% (divider off). 50
r,f
Programmable 16-bit divider with a selectable /2
prescaler allows LVCMOS frequencies below 2 Hz.
(LVCMOS optimized for frequencies <= 125 MHz)
2.3 LVDS AMPLITUDE
NOVATECH INSTRUMENTS
into 50 .
rms
Meets EIA-644A specifications when terminated
into
a
100
SN65LVDS100, or equivalent)
2.4 CONTROL
Output frequency (48-bits), phase (14-bits), CMOS
divider, and amplitude scaling (10-bits) are con-
trolled by a serial port. Settings can be saved in
EEPROM.
2.5 ACCURACY AND STABILITY
Accuracy: < ±1.5ppm at 10-40
additional ±2ppm per year, 18-28
2.6 EXTERNAL CLOCK/REFERENCE IN
Direct external clock frequency range of 250 to
1000 MHz or locked to a 10.0 MHz (±0.01%) refer-
ence. The 425A specifications depend upon the
quality of this signal.
Input Level (50 :
10 MHz Reference: 0.75-1.25 Vrms Sine or LVC-
MOS Square Wave.
External Clock: -3 to +6 dBm sine wave.
2.7 SPECTRAL PURITY
clock)
Phase Noise:<-140 dBc, 10 kHz offset, 10 MHz out.
Spurious:
<-70 dBc below 10 MHz
<-60 dBc below 50 MHz
<-55 dBc below 150 MHz
<-45 dBc below 350 MHz
Harmonic:
<-65 dBc below 1 MHz
<-60 dBc below 10 MHz
<-55 dBc below 25 MHz
<-45 dBc below 50 MHz
<-40 dBc below 150 MHz
<-25 dBc below 350 MHz
2.8 POWER REQUIREMENTS
+4.75 to +5.25 V @ <750 mA. 2.5 mm center-
positive connector on rear panel. AC line (country
dependent) adapter provided.
2.9 SIZE
39 mm H, 107 mm W, 172 mm L, not including con-
nectors.
2.10 CONNECTORS
BNCs for SINE Out, LVCMOS Out, LVDS out, REF
IN. 2.5 mm center positive barrel connector for
Power. DE9 for serial control.
2
differential
load
(driver:
o
C. Stable to an
o
C.
(Typical, 50 load, int.
Rev 1.01, 425A Manual
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