Related Manuals for Radstone PPC7A
Summary of Contents for Radstone PPC7A
- Page 1 (217) 352-9330 | Click HERE Find the Abaco Systems / Radstone PPC7A10 at our website:...
- Page 2 PPC7A Product Manual Publication No. PPC7A-0HH Edition, April 2003 © Radstone Technology PLC Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
- Page 3 Trademarks The Radstone name, Radstone and PowerXtreme logos and are trademarks of Radstone Technology PLC. All other company and product names are acknowledged as being the trademarks or registered trademarks of their respective companies.
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Page 4: Table Of Contents
PPC7A Product Manual Contents Chapter 1 - Introduction ........................1-1 Build Levels .............................1-1 Communications............................1-1 Standards ..............................1-1 Objectives of this Manual ........................1-2 Documentation Audience .........................1-2 Scope of this Manual..........................1-2 Structure of this Manual...........................1-3 Safety Notices ............................1-4 Safety Summary..........................1-4 Ground the Equipment ........................1-4 Do Not Operate in an Explosive Atmosphere................1-4... - Page 5 PPC7A Product Manual Contents ECC Enable Link (E6) ..........................4-4 FLASH Boot Image Select Link (E7 & E8).....................4-4 On-board SCSI Terminator Enable Link (E13) ..................4-4 Enable Front Panel Reset Switch Link (E14)...................4-5 Geographical Addressing/Board ID Links (E11, E2, E12 and E10)............4-5 VME Slave Address Configuration ....................4-6...
- Page 6 PPC7A Product Manual Contents Hard Reset.............................8-4 Soft Reset ............................8-5 VMEbus Remote Reset .........................8-5 Watchdog Reset ..........................8-5 Memory ..............................8-6 Controller ............................8-6 Maps..............................8-6 SDRAM ............................8-6 FLASH............................8-7 VME Programming Option......................8-8 JTAG ................................8-9 JTAG Clock Frequencies ......................8-10 JTAG and PMC...........................8-10 PCI Buses ...............................8-11 Memory/PCI Bridge........................8-11 Ethernet Controller........................8-12...
- Page 7 PPC7A Product Manual Contents Extended ID Register (Port 0x0858)...................8-28 ID Link Register (Port 0x0864) ....................8-29 Motherboard Type Register (Port 0x0866) .................8-30 FLASH Write Protection (Port 0x0868) ..................8-31 FLASH Control Register (Port 0x086E)..................8-32 Control and Status Registers on CS0 .....................8-33 Board ID (Port 0x0) ........................8-33 Last Reset Source (Port 0x2) ......................8-33...
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Page 8: Chapter 1 - Introduction
PPC range of cards such a popular VME card. Build Levels Like all Radstone’s VME products, the PPC7A is available in a range of build styles, form Level 1 (Standard), suitable for a benign office-like environment, right through to Level 5 (Rugged Conduction- cooled), capable of withstanding the harshest of environments. -
Page 9: Objectives Of This Manual
The on-board firmware and other firmware (e.g. drivers, BSPs, ESPs etc.) are described in separate manuals. Documentation Audience This manual is written to cover, as far as possible, the range of people who will handle or use the PPC7A including (but not limited to): •... -
Page 10: Structure Of This Manual
Structure of this Manual This manual is structured in a way that will reflect the sequence of operations from receipt of the PPC7A up to getting it working in your system. Each topic is covered in a separate chapter and each chapter begins with a brief introduction that tells you what the chapter contains. -
Page 11: Safety Notices
Failure to comply with these precautions or with specific Warnings and/or Cautions elsewhere in this manual violates safety standards of design, manufacture and intended use of the equipment. Radstone Limited trading as Radstone Technology assumes no liability for the user’s failure to comply with these requirements. - Page 12 A proper installation in a CE-marked system will maintain the required EMC/safety performance. " CAUTION Only use the PPC7A in backplanes that supply power on both the J1 and J2 connectors. Do not remove the heatsink(s). There are no PROMs or other user-alterable components underneath the heatsink, so users should have no reason to remove it.
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Page 13: Conventions Used In This Manual
Users should not attempt reattachment of the heatsink, as this requires precise torque on the screws attaching the heatsink to the PCB. Over-tightening the screws may cause the heatsink to damage components beneath it (e.g. the main PowerPC processor). Radstone should only carry out removal and re-attachment of the heatsink. -
Page 14: Associated Documents
Associated Documents Due to the complexity of some of the parts used on the PPC7A, it is not possible to include all the detailed data on all such devices in this manual. The following is a list of the specifications and data sheets that provide any additional information required: VME64 Specification ANSI/VITA 1-1994 April 1995. -
Page 15: World Wide Web Sites
VxWorks BSP for PPCx Release Notes, publication number RT5080. World Wide Web Sites Manufacturers of many of the devices used on the PPC7A maintain FTP or world-wide-web sites. Some useful sites are: Motorola PowerX data is available through this site. -
Page 16: Chapter 2 - General Description
The highly integrated nature of the PPC7A makes it a true single board computer. In many ways, the PPC7A resembles a high performance PC motherboard, although in a more rugged, lower profile and more compact form factor. -
Page 17: Features
PCI sub-system expansion to add new, low cost interface capability as required • Two on-board Ethernet controllers giving 10/100BaseT • Radstone COTS software support includes BIT, Boot firmware, BSPs and ESPs (with BCS) for LynxOS/LynxOS HA, VxWorks/Tornado and RTEMS • Wide range of shrink-wrapped application software available •... -
Page 18: Functional Overview
PPC7A Product Manual General Description • 4 off RS232 serial I/O channels up to 115.2 kbaud • 2 off RS485/422/232 software selectable serial I/O channels up to 1 Mbaud • Parallel printer port • 16 bit wide IO interface •... -
Page 19: Processor
The above estimated values are supplied by Motorola Semiconductor, and illustrate the performance and power dissipation of the CPU. Radstone PowerX SBCs are designed to take the processor, providing a balanced general-purpose platform. The actual performance and power dissipation may vary depending on the application being run and resource usage of the configured system. -
Page 20: Pci
STD-1553, asynchronous serial, Fast Ethernet, FLASH memory, Fibre Channel and ATM, all fully compliant with the IEEE P1386.1 standard. Using the PCI to PCI bridge device on the PMCPCI bridge card (see overleaf), the PPC7A can maintain concurrent bus operation. This allows applications using PMCs for routing and communications to operate efficiently and in parallel without being blocked. -
Page 21: Memory
Two PMC slots are provided as standard on the PPC7A. These PCI slots are 64 bits wide and run at 66 MHz. If a PCI card is fitted that is not capable of running at 66 MHz, then the PPC7A will reduce the frequency to 33 MHz for both PCI slots. -
Page 22: Vmebus Interface
PPC7A Product Manual General Description amount of cache that can be fitted depends on the CPU that is fitted to the PPC7A, for example the MPC7455 limits the external cache to 2 Mbytes. VMEbus Interface The Tundra Universe II chip provides a full master/slave VMEbus interface. Features include: •... -
Page 23: Software Support
Memory or other speed and feature enhancements are seamlessly absorbed by the Boot firmware, giving the same look and feel to the O/S and the user application as the Radstone hardware models advance. This allows the constant use of latest technology in required areas without system impact. Where particular operating systems define the use of alternate boot methods (e.g. -
Page 24: Build Styles
I/O file system. The full range of facilities are supported by BSPs for all Radstone CPU types, which have been validated by both Radstone and Wind River for the greatest confidence and ease of use. To complement the BSPs, many of Radstone’s I/O and graphics products are also supported by libraries and drivers. -
Page 25: Level 2
PPC7A Product Manual General Description Level 2 As Level 1, but conformally coated and 100% tested in manufacture to provide an extended operating range. Level 3 Level 3 boards are intended for applications that have extended temperature, shock and vibration requirements, but can be served by conventional, forced-air-cooled, racking systems. -
Page 26: Chapter 3 - Inspection
Figure 3.1 – Board Handling Product Identification Radstone hardware products are identified by labels at strategic positions. You can cross-check these against the Advice Note provided as a separate note with your delivery. On the outside of the shipping box, and the antistatic bag, there is a label similar to the following: On the card within the antistatic bag, there is an identifying label, similar to the following, attached to the printed wiring board. -
Page 27: Inspection
Inspection 1. Visually inspect the board for any damage and loose or dislodged components. 2. Report any defects you detect to Radstone. 3. Referring to Chapter 4 – Configuration, visually inspect the board to ensure that the default configuration is correct and that there are no loose or missing jumpers: Edition Artisan Technology Group - Quality Instrumentation ... -
Page 28: Chapter 4 - Configuration
PPC7A Product Manual Chapter 4 - Configuration This chapter describes the configuration of links on the PPC7A. The board is delivered with push-on jumper links, but for more rugged or military applications, link pins must be connected using wire wraps. -
Page 29: Default Link Settings
This link selects the voltage of the standby supply to the I²C RTC (DS1337). As the normal VME standby voltage is 5 Volts, the link should not normally be fitted. However, the PPC7A can be linked to use a backup supply of 3.3 Volts. -
Page 30: Flash Write Enable Links (E3 And E9)
PPC7A Product Manual Configuration FLASH Write Enable Links (E3 and E9) Each link enables or disables erasure/reprogramming of a section of the FLASH. E3 controls the User FLASH and E9 controls the System FLASH. See Chapter 8 for details of FLASH operation. -
Page 31: Ecc Enable Link (E6)
Disable on-board SCSI terminators If you are using the SCSI bus, you are recommended to locate the PPC7A at one end and enable the terminator by fitting link E13. If you want to use the PPC7A somewhere other than at the end of the SCSI bus, ensure that E13 is not fitted. -
Page 32: Enable Front Panel Reset Switch Link (E14)
Enable reset switch Note: The function of this link is the opposite of most other Radstone PPC cards. Geographical Addressing/Board ID Links (E11, E2, E12 and E10) These links form a 4-bit board ID that may be read from the ID Link register (see Chapter 8). The links... -
Page 33: Vme Slave Address Configuration
Disabled Changing the default power-up options requires surface-mount rework tools and would normally only be done at the factory. Further details are available from technical support at Radstone. Edition Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com... -
Page 34: Chapter 5 - Connectors
PPC7A Product Manual Chapter 5 - Connectors This chapter gives the pinouts and signal descriptions for the connectors on the PPC7A. The following table shows the function of the connectors on the PPC7A: ONNECTOR UNCTION VMEbus VMEbus PMC site 1 I/O... -
Page 35: P1 (Vmebus) Connector Pinout
PPC7A Product Manual Connectors P1 (VMEbus) Connector Pinout BBSY~ BCLR~ ACFAIL~ BG0IN~ BG0OUT~ BG1IN~ BG1OUT~ BG2IN~ BG2OUT~ SYSCLK BG3IN~ SYSFAIL~ GA0~ BG3OUT~ BERR~ GA1~ DS1~ BR0~ SYSRESET~ DS0~ BR1~ LWORD~ GA2~ WRITE~ BR2~ BR3~ GA3~ DTACK~ GA4~ IACK~ IACKIN~ IACKOUT~... -
Page 36: P2 Connector Standard Pinout
PPC7A Product Manual Connectors P2 Connector Standard Pinout The following P2 pinout is correct if the J24 connector is not fitted. FLASH_WREN~ DB0~ (SCSI) RX0+ COM3_TXD_A DB1~ (SCSI) RX0- COM3_TXD_B EXT_RESET~ DB2~ (SCSI) Reserved TX0+ COM3_RXD_A DB3~ (SCSI) TX0- COM3_RXD_B... -
Page 37: P2 Connector Pinout (When J24 Is Fitted)
PPC7A Product Manual Connectors P2 Connector Pinout (when J24 is fitted) The following P2 pinout is correct if the J24 connector is fitted. PMC2_IO_2 DB0~ (SCSI) RX0+ PMC2_IO_1 DB1~ (SCSI) RX0- PMC2_IO_3 PMC2_IO_5 DB2~ (SCSI) Reserved TX0+ PMC2_IO_4 DB3~ (SCSI) -
Page 38: Alternate P2 Pinout For Gpio Pins
PPC7A Product Manual Connectors Alternate P2 Pinout for GPIO Pins The following pinout table shows alternate P2 Row C pin functions. LOPPY GPIO0 RDATA~ STROBE~ GPIO1 WGATE~ LPTD0 GPIO2 WDATA~ LPTD1 GPIO3 HDSEL~ LPTD2 GPIO4 FD_DIR~ LPTD3 GPIO5 STEP~ LPTD4... -
Page 39: Vmebus Signal Descriptions
PPC7A Product Manual Connectors VMEbus Signal Descriptions The VMEbus signals occupy rows a, b and c of the P1 connector and row b of the P2 connector. NEMONIC IGNAL ESCRIPTION Address Bus (bits 1 to 15). Address lines that are used to broadcast a short address A01 to A15 Address Bus (bits 16 to 23). -
Page 40: P2 I/O Signal Descriptions
Geographic Address. These are used to set the slave VME address of the board. GA0~ to GA3~ may be set to GA0~ to GA4~ zero by fitting links E4, E8, E10 and E5 respectively. When GA4~ is not connected, a pull-up resistor on the PPC7A pulls the signal high P2 I/O Signal Descriptions NEMONIC... - Page 41 PPC7A Product Manual Connectors P2 I/O Signal Descriptions Continued NEMONIC IGNAL ESCRIPTION BUSY Parallel port BUSY nACK Parallel port ACK D1 to D8 Parallel port data bits nSTROBE Parallel port STROBE TX0±/TX1± 10/100BaseT transmit data 10/100BaseT receive data RX0±/RX± FLASH_WREN~...
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Page 42: P0 Connector Pinout
P0 is routed to J14 and partially to J24. Note: Due to the large amount of I/O required to be handled by the PPC7A, Type B connectors are preferred to the Type A (80-pin) shown overleaf, and are fitted by default no particular type is specified. -
Page 43: Type A (80-Way)
P0 is routed to J14. Note: Due to the large amount of I/O required to be handled by the PPC7A, Type B (95-way) connectors are preferred to Type A, and are fitted by default no particular type is specified. REDLED~... -
Page 44: P0 I/O Signal Descriptions
PPC7A Product Manual Connectors P0 I/O Signal Descriptions NEMONIC IGNAL ESCRIPTION Driven identically to the corresponding LED except that this signal has a separate REDLED~ buffer with a 180Ω series resistor Driven identically to the corresponding LED except that this signal has a separate GREENLED~ buffer with a 180Ω... -
Page 45: Pmc Connector Pinouts
PPC7A Product Manual Connectors PMC Connector Pinouts J11/J21 and J12/J22 give the signals for 32-bit PCI. J13/J23 give the signals for 64-bit PCI and J14/J24 give the user I/O signals. J11 and J21 IGNAL IGNAL -12V INTA~ INTB~ INTC~ BUSMODE1~... -
Page 46: J12 And J22
AD07 REQB~ 3.3V† GNTB~ ACK64~ 3.3V† † The 3.3V pins are connected to the PPC7A main 3.3V supply. " CAUTION Do not fit a PMC that requires more than 8 watts from the 3.3V supply. Edition 5-13 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com... -
Page 47: J13 And J23
PPC7A Product Manual Connectors J13 and J23 IGNAL IGNAL Reserved (PCI) CBE7~ CBE6~ CBE5~ CBE4~ V (I/O) PARR64 AD63 AD62 AD61 AD60 AD59 AD58 AD57 V (I/O) AD56 AD55 AD54 AD53 AD52 AD51 AD50 AD49 AD48 AD47 AD46 AD45 V (I/0) -
Page 48: Pmc Signal Descriptions
Test Data Out. Data from a PMC JTAG chain Note: The PPC7A supports PMC clocking at speeds up to 66 MHz. However, if a PMC is fitted to the PPC7A that does not support the 66 MHz clocking speed, then both sites are limited to 33 MHz. -
Page 49: J14 Pmc I/O
PPC7A Product Manual Connectors J14 PMC I/O J14 is routed to P0. IGNAL IGNAL PMC1_IO_1 PMC1_IO_2 PMC1_IO_3 PMC1_IO_4 PMC1_IO_5 PMC1_IO_6 PMC1_IO_7 PMC1_IO_8 PMC1_IO_9 PMC1_IO_10 PMC1_IO_11 PMC1_IO_12 PMC1_IO_13 PMC1_IO_14 PMC1_IO_15 PMC1_IO_16 PMC1_IO_17 PMC1_IO_18 PMC1_IO_19 PMC1_IO_20 PMC1_IO_21 PMC1_IO_22 PMC1_IO_23 PMC1_IO_24 PMC1_IO_25 PMC1_IO_26... -
Page 50: J24 Pmc I/O And Partial P2 Option
PPC7A Product Manual Connectors J24 PMC I/O and Partial P2 Option J24 may be partially routed to the P2 connector, depending on the build option. If used, then COM3 and COM4 are no longer routed to P2. P2 now has the connections shown in the following table:... -
Page 51: P10 Pld Connector Pinout
PPC7A Product Manual Connectors P10 PLD Connector Pinout P10 is the programming JTAG chain this is normally for factory use. ESCRIPTION PLD_TDO PLD_TDI KEYWAY PLD_TMS PLD_TCK For more information on JTAG, see Chapter 8. P8 RISCWatch Connector Pinout P8 is the RISCWatch connector allowing the connection of software debugging tools that use the processor’s JTAG port to control the operation of the processor. -
Page 52: P8 Signal Descriptions
PPC7A Product Manual Connectors P8 Signal Descriptions IGNAL ESCRIPTION TDO_CPU Processor JTAG Test Data Out EMU~ When connected to GND, creates QACK~ to the processor. This connection should be made with an emulator TDI_CPU Processor JTAG Test Data In TRST~ Processor JTAG Test Reset +3.3V PULL-UP... -
Page 53: Chapter 6 - Front Panel
Radstone will fit a blanking plate in the slot(s) for EMC protection. If you are fitting a non-Radstone PMC, it must comply with the standard for rugged, conduction-cooled PMCs to ensure that it mates correctly with the PPC7A mechanics. This will be the case for Radstone PMCs. - Page 54 PPC7A Product Manual Front Panel Figure 6-1. PPC7A Front Panel Edition Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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Page 55: Chapter 7 - Installation And Power-Up
PPC7A Product Manual Chapter 7 - Installation and Power-up This chapter describes the installation of PMC cards on the PPC7A and the installation of the PPC7A board in a system. It then describes power-up of the board. PMC Installation Two single width (or one double-width) PMCs may be fitted to the PPC7A, which is keyed to accept only 5V PMCs. -
Page 56: Board Installation
Installation and Power-up Board Installation Radstone enclosures usually have two sets of links in the J1 (VMEbus) half of the backplane. The upper set of four links configures the Bus Grant (BGx) daisy chain. The lower link configures the Interrupt Acknowledge (IACK) daisy chain. -
Page 57: System Configuration Suggestions
E13. If you want to use the PPC7A somewhere other than at the end of the SCSI bus, ensure that E13 is not fitted. Fitting E13 when the PPC7A is not located at the end of a SCSI bus may cause erroneous SCSI operation. -
Page 58: Power-Up
If you need to operate a conduction-cooled board on an extender card, maintain an airflow of at least 300 feet/minute over it, by the use of a suitable fan. Before plugging the PPC7A into a development rack, you should first check the rack’s backplane configuration links. -
Page 59: Power-Up Routine
PPC7A Product Manual Installation and Power-up Power-up Routine The power-up routine depends on the firmware options fitted, as shown in the following diagram: BIT is described in the PPC BIT Release Notes, publication number RT5111. The Boot firmware is described in the PPC Boot Firmware Manual, publication number RT5078. -
Page 60: Chapter 8 - Functional Description
Figure 8.1 – Block Diagram Notes: Due to the increasingly short lifetimes of system components, the I/O devices used on the PPC7A are not guaranteed to remain fixed in the future. Hardware should be accessed only through mechanisms provided by the Operating System’s “Hardware Independence”... -
Page 61: Powerpc Processor
PPC7A Product Manual Functional Description PowerPC Processor MPC7455 The PPC7A is based around the MPC7455 PowerPC chip. This device contains: • A 32-bit implementation of the PowerX architecture • 32 Kbytes, 8-way set associative instruction and data caches • On chip 256 Kbytes of L2 cache •... -
Page 62: Mpc7410
PPC7A Product Manual Functional Description MPC7410 The PPC7A is based around the MPC7410 PowerPC chip. This device contains • A 32-bit implementation of the PowerX architecture • 32 Kbytes, 8-way set associative instruction and data caches • A separate 64-bit wide, two-way set associative L2 cache bus The processor has a 32-bit physical address bus and a 64-bit data bus. -
Page 63: Resetting The Ppc7A
Functional Description Resetting the PPC7A There are two types of reset that may be applied to the PPC7A: ‘Hard’ and ‘Soft’. Hard Reset This causes the processor to begin executing code from address 0xFFF0 0100 in the System FLASH. By fitting a hardware jumper (E2), the System FLASH addresses may be passed to the VME instead of the FLASH. -
Page 64: Soft Reset
E14. The standard boot firmware does not support the use of soft reset. VMEbus Remote Reset Another VME master may reset the PPC7A via the Universe II control registers. This causes a hard reset. Watchdog Reset If enabled and triggered (via the Watchdog control register), the watchdog will cause a hard reset unless re-triggered (via the Watchdog Trigger Register) every 1.6 seconds. -
Page 65: Memory
The Galileo GT64260 device provides an SDRAM memory controller and a FLASH interface. Maps The PPC7A supports programmable memory maps. No memory maps are provided in this manual as no memory locations are fixed in hardware. Please refer to the manuals for the software that is installed on the PPC7A for more information. -
Page 66: Flash
Main BOOT This area is used as the main default boot area of the PPC7A. This area would be the area that the user would put his boot firmware. This area is selected for booting by not fitting E7 (BOOT_ALTERNATE) and E8 (BOOT_RECOVERY) links. -
Page 67: Vme Programming Option
VME Programming Option Fitting link E4 (see Chapter 4) allows the PPC7A to have new boot firmware programmed via the VMEbus. This link is intended for factory use only. Normally, if the Boot firmware gets corrupted the Recovery boot option should be used to restore the Boot firmware. -
Page 68: Jtag
All of the JTAG chain connections are routed to connector P10 (see Chapter 5 for more details). There are three chains on the PPC7A. One chain is solely for the purpose of programming the CPLD device, which contains various functions, including the main PPC7A ISAbus registers. This device is programmed via JTAG. -
Page 69: Jtag Clock Frequencies
The “MAIN” JTAG chain from J11 & J12 visits the other PMC site. These individually auto-bypass if a PMC is not fitted at the site. To achieve this, the PPC7A has BUSMODE2 to BUSMODE4 wired to 1, 0, 0 respectively. This effectively interrogates the PMC site as to whether it has a PCI compliant card fitted. -
Page 70: Pci Buses
Mbytes/second between PCI agents. The PCI bus structure of the PPC7A is shown below: Figure 8.2 – PCI Bus Diagram Memory/PCI Bridge The Memory/PCI Bridge on the PPC7A is provided by a Galileo GT64260 Discovery device: • This device provides: •... -
Page 71: Ethernet Controller
SCSI bus and the terminator should only be enabled if the PPC7A is at the end of the SCSI bus. Otherwise, the PPC7A must be at the end of the SCSI bus and the terminator must be enabled. -
Page 72: South Bridge
Apart from the south bridge, there are no other ISAbus masters in the PPC7A architecture. PMC Sites The PPC7A has two sets of connectors ({J11, J12, J13, J14} and {J21, J22, J23, J24}) that allow standard PMCs to be connected to the PCI bus. The PPC7A can accept either air-cooled or conduction cooled PMCs, as long as adequate cooling is provided. -
Page 73: Keyboard And Mouse Controller
• Interprocessor communications • Block transfer support Appendix A details the VMEbus compliance and basic VMEbus performance of the PPC7A. Note: The Universe II does not self-address. VMEbus Master Access Four general-purpose, software-programmable PCI slave images are available for access to the VMEbus. -
Page 74: Vmebus Slave Access
One further, special purpose, VMEbus slave image, the Register Access Slave Image, allows a VMEbus master to access to the Universe II control and staus registers. VMEbus slave accesses to the PPC7A may be coupled, write posted or pre-fetched block read. •... -
Page 75: Semaphore Register
PPC7A Product Manual Functional Description Semaphore Register The Universe II provides a 32-bit register containing four semaphores, one in each byte. • Each of the four semaphores is a 7-bit data field plus a 1-bit lock field • Ownership of the semaphore is obtained by writing a unique value to the 7-bit field while setting the lock bit •... -
Page 76: Vmebus Retries
VMEbus Interface Configuration section in Chapter 4 for the default options. Watchdog Timers The PPC7A contains a Maxim 706 microprocessor supervisory circuit with a watchdog timer. Once enabled, this timer must be re-triggered every 1.6 seconds or a hard reset results. The trigger control registers is 0x82C and is enabled via Control register 0x828. -
Page 77: Software Programmable Leds
Functional Description Software Programmable LEDs The PPC7A has the following software programmable LEDs: Control register 0x820 provides four signals, which are connected to four of the LEDs. There is a separate control bit for each LED. Three are visible in the front panel (DS1/2/3) and also on the back of the board as DS12/13/14, together with DS11. -
Page 78: Control And Status Registers
Where: R/W = Read/Write RO = Read Only WO = Write Only The control and status registers exist on the PPC7A for controlling or reading the status of the hardware. The addresses are as seen by the processor. Edition 8-19... -
Page 79: Memory Configuration Register (Port 0X0804)
PPC7A Product Manual Functional Description Certain registers are described in detail in the following pages. The others are registers in the ISA Bridge or other major devices, which are described in the detail in the appropriate device data sheet (which will also give the appropriate ‘Type’... -
Page 80: Memory Configuration Extend Register (Port 0X0806)
PPC7A Product Manual Functional Description Memory Configuration Extend Register (Port 0x0806) This register provides size information for the SDRAM and FLASH memory banks. MSB = D0, LSB = D7 D0 and D1: SDRAM Bank size 0 = 64 Mbytes 1 = 128 Mbytes... -
Page 81: Scsi Activity Led Register (Port 0X0808)
PPC7A Product Manual Functional Description SCSI Activity LED Register (Port 0x0808) This register allows control of the SCSI activity LED. MSB = D0, LSB = D7 D0 to D6: Reserved. SCSI activity LED 0 = LED off 1 = LED on Equipment Present Register 1 (Port 0x080C) This register provides information on hardware options and the state of the SCSI Terminator power fuse. -
Page 82: Equipment Present Register 2 (Port 0X080E)
PPC7A Product Manual Functional Description Equipment Present Register 2 (Port 0x080E) This register provides information on hardware options fitted to the PPC7A. MSB = D0, LSB = D7 Universe II Fitted 0 = Not fitted 1 = Fitted Reserved, always reads ‘0’... -
Page 83: Equipment Present Register 3 (Port 0X0810)
PPC7A Product Manual Functional Description Equipment Present Register 3 (Port 0x0810) This register provides information on hardware options fitted to the PPC7A. MSB = D0, LSB = D7 D0 to D3: Reserved. Always reads ‘0’ PMC IO voltage 0 = 5 Volt 1 = 3.3 Volt... -
Page 84: Led Register (Port 0X0820)
PPC7A Product Manual Functional Description LED Register (Port 0x0820) This register provides control for the 4 user LEDs fitted to the PPC7A. MSB = D0, LSB = D7 SCSI_TERM_REQ 0 = SCSI terminator not required (SCSI link not fitted) 1 = SCSI terminator required (SCSI link fitted) -
Page 85: Coms Register (Port 0X0824)
PPC7A Product Manual Functional Description COMs Register (Port 0x0824) This register provides control for COMs 3 & 4, for the Clocks and interface configuration. MSB = D0, LSB = D7 COM3_CLK_EN, this bit enables the TSCLK3 signal out on to COM3_TT (transmit clock) -
Page 86: Rts Register (Port 0X0826)
Enabled Enabled by RTS4 Enabled by RTS4 & stretched Watchdog Register (Port 0x0828) This register controls the watchdog resets features of the PPC7A. MSB = D0, LSB = D7 Last reset was a watchdog 0 = Normal reset 1 = Last board reset was caused by a watchdog timeout... -
Page 87: Watchdog Trig (Port 0X082C)
Note: Data written is not used and Reads don’t trigger the watchdog. Board Revision Register (Port 0x0854) This register provides information on the build state of the PPC7A. MSB = D0, LSB = D7 D0 to D2: Number revision of hardware build state... -
Page 88: Id Link Register (Port 0X0864)
PPC7A Product Manual Functional Description ID Link Register (Port 0x0864) This register allows you to read the Board ID links (E4, E5, E8 and E10) or the VME Geographical address pins. MSB = D0, LSB = D7 Reserved Reserved Reserved... - Page 89 Motherboard Type Register (Port 0x0866) This register provides information on the type of motherboard and SDRAM ECC operation. The bits used in this register are compatible with the other members of the current Radstone PPC product range. MSB = D0, LSB = D7...
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Page 90: Flash Write Protection (Port 0X0868)
PPC7A Product Manual Functional Description FLASH Write Protection (Port 0x0868) This register provides information on the FLASH write protection. MSB = D0, LSB = D7 FLASH write enable link 0 = link not fitted 1 = link fitted Status of the P2 or P0 FLASH_WREN~ signal... -
Page 91: Flash Control Register (Port 0X086E)
This register provides status and control signals for the Boot sections of the FLASH devices. When the PPC7A is reset, this register is reset to reflect the status of the BOOT links (E8, E4 & E7), after boot software can then override these link settings by writing to bits D5 & D7 in this register. -
Page 92: Control And Status Registers On Cs0
0x0E = PPC7A - 7410/755 0x0F = PPC7A – 745x 0x10 = PPC7FW (MPC7410 with Firewire) All others patterns mean the board is not a PPC7A Last Reset Source (Port 0x2) This register provides information about what caused the last reset. -
Page 93: Reset Register (Port 0X3)
D4 to D7: 4 bit register Board ID String (Port 0x4 to 0x7) This register provides a board ID string, which shows 'PPC7A' when read as a 32 bit value. Port 0x4 MSB = D0, LSB = D7 D0 to D7:... -
Page 94: Interrupts And Error Reporting
Machine Check Exception The South Bridge can be configured the signal NMI on certain conditions. The hardware on the PPC7A routes this signal to the CPU as the MCP~ (Machine Check) interrupt. The South Bridge can drive this signal due to the following conditions: •... -
Page 95: External Interrupt (Int~)
The processor external interrupt pin (INT~) is asserted for a pending interrupt from the interrupt controller in the South Bridge. Interrupt priorities and modes are assigned as the firmware running on the PPC7A. PCI Interrupts There are 4 interrupt lines for the PMC expansion slots on the motherboard and the PMC carrier. These are connected to the PIRQ~ inputs of the interrupt controller. -
Page 96: Pci Configuration
PPC7A Product Manual Functional Description PCI Configuration The boot process must configure the base address and space type (memory or I/O) of all the PCI attached peripherals. The memory requirements of each PCI device are given in the appropriate device descriptions in this chapter. -
Page 97: Chapter 9 - Technical Assistance
PPC7A Product Manual Chapter 9 - Technical Assistance Radstone Contact Information In the unlikely event that you experience problems with your PPC7A, for assistance please contact Radstone’s Technical Help Line on: +44 1327 359804 outside the UK 01327 359804 in the UK... -
Page 98: Troubleshooting
E13. If you want to use the PPC7A somewhere other than at the end of the SCSI bus, ensure that E13 is not fitted. Fitting E13 when the PPC7A is not located at the end of a SCSI bus may cause erroneous SCSI operation. -
Page 99: Appendix A - Specifications
PPC7A Product Manual Appendix A - Specifications This appendix provides the detailed technical specification for the PPC7. It covers the following items: • VMEbus compliance • Local resources • EMC regulatory compliance and safety • Power requirements • Reliability/Mean Time Between Failures •... -
Page 100: Vmebus Compliance
PPC7A Product Manual Specifications VMEbus Compliance The PPC7A conforms to the ANSI/VITA 1-1994 standard for VME64. Master: A16, A24 and A32 ADO, ADOH A16:LCK, A24:LCK, A32:LCK D08(EO), D08(EO):RMW, D08(EO):BLT D16, D16:RMW, D16:BLT D32, D32:RMW, D32:BLT, D32:UAT D64:MBLT Slave: A16, A24 and A32... -
Page 101: Local Resources
PPC7A Product Manual Specifications Local Resources Processor PowerPC 745x at 500 MHz or above. 64 to 512 Mbytes with ECC. SDRAM L2 or L3 Cache 1 to 4 Mbyte on private cache bus. Totally integrated 2D graphics processor with 2Mbytes of Graphics graphics SRAM on chip. -
Page 102: Emc Regulatory Compliance And Safety
It may not be possible to support all combinations of SDRAM and PMCs within this limit. The PPC7A uses the undefined pins (rows a, c, d and z) of the VMEbus P2 connector for I/O and power/ground connections. 3.3V is connected to both of the PMC sites. -
Page 103: Reliability (Mtbf
PPC7A Product Manual Specifications Reliability (MTBF) The following table shows the calculated MTBFs for the PPC7A-1BA-10: Fail Rate Environment MTBF (H OURS (Failures Per Million Hours) Ground benign 30°c 6.298724 158,762 14.72659 67,904 Ground fixed 40°c 26.94278 37,116 Ground mobile 45°c Naval sheltered 40°c... -
Page 104: Mechanical Construction
The approximate weight of the PPC7A is 680g. Dimensions The PPC7A is constructed on a multi-layer double Eurocard and conforms to the dimensions specified in the ANSI/VITA 1-1994 specification. The dimensions shown below are in millimetres, with inches (in parentheses) for general guidance only. -
Page 105: Ordering Information
P0 options are available on all build levels. Due to the large amount of I/O required to be handled by the PPC7A, Type B (95-way) connectors are preferred to Type A (80-pin), and are fitted by default no particular type is specified. -
Page 106: Pmcs
Radstone directly or your nearest Sales Office. Note: Level 1 PMCs (from Radstone and third parties) can be used on both build levels (1 and 2) of the PPC7A, even if the PMC does not meet the extended temperature and environmental requirements of level 2. -
Page 107: Operating Systems
INTEGRITY Please contact Radstone for more details. P2 I/O Module The Backplane Transition Module for the PPC7A is the P25X606, illustrated below. Compatible Rear I/O modules are shown in parenthesise. For installation instructions, refer to the I/O Module Installation Guide, Publication Number RT5154. - Page 108 PPC7A Product Manual Specifications Pin Assignments For P25X606 pin assignments, refer to the schematic diagram below. P1 - 8 bit SCSI J2 - Backplane Connector SCSI_DB0 SCSI_DB1 FLASH_WREN~ RX0_PLUS COM3_TXD_A SCSI_DB0 SCSI_DB2 RX0_NEG COM3_TXD_B SCSI_DB1 SCSI_DB3 EXTRESET~ TX0_PLUS COM3_RXD_A SCSI_DB2...
- Page 109 PPC7A Product Manual Specifications Ordering Information P25X606 Additional Signals 0 = Spares unconnected 1 = Spares connected to P2 2 = Spares connected to VCC COM 3/COM4 RS422 Termination 0 = No termination 1 = COM3 terminated, COM4 not terminated...
- Page 110 CR/CSR Configuration ROM/Control and Status Register. Line Replaceable Unit. PPC7A Radstone’s PowerPC-based processor card. The PPC7A is based on the PowerPC 745x/7410 processor with integral L3/L2 cache controller and uses SDRAM. Edition Glossary i Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
- Page 111 PPC7A Product Manual Index Controller ............ 8-12 Antistatic Precautions ........3-1 Applications............1-1 Floppy Disk Controller ............ 8-13 Front Panel............6-1 Functional Overview......... 2-3 BCS ..............2-8 BIT..............2-8 Board ID ............3-1 Register............8-29 Heatsink ............1-5 Boot Firmware..........2-8 Build Styles ............
- Page 112 PPC7A Product Manual Index Controller............8-6 SCSI FLASH ............8-7 Processor............. 8-12 Maps ............. 8-6 Terminator ......... 8-12, 8-22, 9-2 SDRAM............8-6 Semaphores............. 8-16 MTBF .............. A-5 Serial I/O............8-13 Software Support ..........2-8 System Controller ........... 8-14 Operating Systems..........2-8 Ordering Information........
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