1. Manuals
  2. Brands
  3. Radstone Manuals
  4. Single board computers
  5. PME 68-1B
  6. Manual

Radstone PME 68-1B Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Radstone Technology plc
Water Lane,
Towcester,
Northants.,
NN12 7JN
Telephone:
0327 50312
Telex:
31628
© Radstone Technology plc 1990
Issue 1 © The Plessey Company plc 1985
Issue 2 © The Plessey Company plc 1987
Issue 3 © The Plessey Company plc 1988
Issue 4 © Radstone Technology plc 1989
This publication is issued to provide outline information only which (unless agreed by the
Company in writing) may not be used, applied or reproduced for any purpose or form part
of any order or contract or be regarded as a representation relating to products or services
concerned. The Company reserves the right to alter without notice the specification, design,
price or conditions of supply of any product or service.
January 1990
PME 68-1B Manual
Publication No. 421/HH/23144/000
RADSTN G
Rev. 2
Issue 5

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PME 68-1B and is the answer not in the manual?

Questions and answers

Related Manuals for Radstone PME 68-1B

Summary of Contents for Radstone PME 68-1B

  • Page 1 Issue 2 © The Plessey Company plc 1987 Issue 3 © The Plessey Company plc 1988 Issue 4 © Radstone Technology plc 1989 This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to products or services concerned.
  • Page 2 RADSTONE the RADSTONE symbol, PME, and PLUM are trademarks of Radstone Technology plc. VERSAdos is a trademark of Motorola. Board Identification All Radstone baoards can be identified by a label fitted to the component side of P1. MADE IN ENGLAND SERIAL NUMBER REV NO.

  • Page 3: Table Of Contents

    PME68-1B Manual Table of Contents Chapter 1 - Introduction Introduction ......................1 Operational Overview ..................7 Features ......................7 I/O Facilities ....................8 Memory ......................8 Real Time Operation ................... 8 Chapter 2 - Specification General ......................... 9 Operating......................10 MTBF ........................
  • Page 4 PME68-1B Manual VMEbus Arbitration ..................36 Using PME 68-1B as the System Bus Arbiter........... 37 Bus Release Functions ................38 VMEBUS Interface ................... 39 SYSCLK Signal .................... 39 SYSRESET* Signal ..................39 RESET Switch ....................39 SYSFAIL* Signal ..................39 Address Modifier Codes ................
  • Page 5 PME68-1B Manual Chapter 5 - PME68/Monitor Software Capabilities ..................75 General System Overview.................. 77 Power-Up Sequence ..................77 RESET Switch ....................77 ABORT Switch....................77 Vectors and Errors..................78 Interrupt Level Assignment................. 79 Return to the Monitor .................. 80 The HALT Indicator ..................80 PME68/Monitor Memory Map ..............
  • Page 6 PME68-1B Manual Mnemonics and Delimiters ................. 109 Character Set ....................110 Source Code Format..................110 Assembler Language Format ..............110 DC.W Define Constant Directive .............. 112 Entering and Modifying Source Programs ..........112 Calling the Assembler/Disassembler ............112 Program Input....................113 Disassembled Program Listings..............

  • Page 7: Introduction

    PME 68-1B Manual Chapter 1 - Introduction The PME 68-1B CPU is a single board computer which combines a powerful 16 bit mi- croprocessor, the Motorola 68000, with 128k or 512k bytes of dynamic RAM (DRAM), up to 256k bytes of EPROM or EPROM + SRAM, a programmable real time clock, plus three serial and one parallel input/output (I/O) interfaces.
  • Page 8 PME 68-1B Manual Figure 1 The PME 68-1B Board Photograph not available in PDF Page 2 Issue 5...
  • Page 9 10 MHz 68000, 512k bytes of DRAM 421/1/23144/103 This manual provides a general operating description of all variants of the PME 68-1B and includes information for installation and troubleshooting in Chapter 4, plus details of the PME68/Monitor in Chapter 5.
  • Page 10 PME 68-1B Manual Figure 2 The PME 68-1B Front Panel PME 68-1B RESET ABORT HALT LED REMOTE Port 3 (P5) TERMINAL Port 1 (P4) HOST Port 2 (P3) RADSTONE TECHNOLOGY Page 4 Issue 5...
  • Page 11 PME 68-1B Manual Figure 3 PME 68-1B Functional Block Diagram RESET Control Interrupt ABORT VMEbus VMEbus Control HALT Arbiter Arbitration Logic VMEbus REMOTE Data Interface Address ACIA Wire- Port 3 Wrap (P5) Wire- Wrap 6850 68000 8/10 MHz. Battery Back-up...
  • Page 12 PME 68-1B Manual Figure 4 Component L ayout Diagram Page 6 Issue 5...

  • Page 13: Operational Overview

    I/O devices. All other addresses are external on the VMEbus. The PME 68-1B board contains a number of features that allow it to act as the CPU of a powerful system, one of a number of CPUs in a multi-processor system, or as a single board computer.

  • Page 14: I/O Facilities

    PME 68-1B Manual I/O Facilities PME68-1B boards have three RS-232C interfaces, identified as Terminal (Port 1), Host (Port 2) and Remote (Port 3) as shown in Figures 2 and 3. Port 1 (connector P4) may be connected to a standard terminal to load and debug user programs under control of the Monitor firmware.

  • Page 15: Chapter 2 - Specification

    PME68-1B Manual Chapter 2 - Specification General Microprocessor Motorola 68000L Type 8 MHz on Variants 100 and 102 10 MHz on Variants 101 and 103 Bus Compliance VMEbus Rev. C.1 Data D08, D16 Address A16, A24 Parallel I/O and Timer 68230 type PIT 16 data lines and 8 control lines, configurable as a Centronics type parallel interface...

  • Page 16: Operating

    20g for 6ms (half sine) when mounted in a suitable racking system MTBF The calculated mean time between failures for the PME 68-1B is 80,000 hrs. The failure rates used in this calculation have been derived from the British Telecom Reliability Handbook using method HRD4, MIL-HDBK-217D and in-house data.

  • Page 17: Chapter 3 - Functional Description

    Hardware Overview Front Panel The front panel of the PME 68-1B is shown in Figure 2 and contains: Reset Switch; a toggle switch, that is user defined to carry out a general VMEbus reset or a reset of all on-board devices only.

  • Page 18: 68000 Hardware Description

    PME68-1B Manual 68000 Hardware Description Processor The 68000 processor contains sixteen 32-bit registers, one 32-bit program counter and a 16 bit status register. The first eight registers (D0 to D7) are used as data registers for byte (8-bit), word (16-bit) and long word (2 x 16-bit) data operations. The set of seven address registers (A0 to A6) and the supervisor stack pointer may be used as software stack pointers and base address registers.
  • Page 19 PME68-1B Manual Table 1 68000 Vector Table Vector Address No.(s) Decimal Space Assignment Reset: Initial SSP Reset: Initial PC Bus Error Address Error Illegal Instruction Z ero Divide CHK Instruction TRAPV Instruction Privilege Violation Trace Line 1010 Emulator Line 1111 Emulator Unassigned (Reserved) Unassigned (Reserved) Unassigned (Reserved)

  • Page 20: Memory

    PME68-1B Manual Memory Figure 5 Memory Map of the PME 68-1B 000 000 ROM Initialisation Vectors from SYSTEM EPROM 000 007 000 008 SYSTEM DRAM Area (Reserved) 000 FFF 001 000 USER DRAM Area (128k byte: variants 100 and 101)

  • Page 21: Ram Area

    PME68-1B Manual RAM Area The on-board dynamic RAM area is used for the exception vector table of the CPU, as a scratch pad RAM for the Resident Monitor and for user program/data. The RAM area has a capacity of 128k bytes on PME68-1B/100 and /101 and 512k bytes on /102 and /103. Typical access time is 280ns if no refresh cycle is taking place.
  • Page 22 PME68-1B Manual EPROM/SRAM Area The PME 68-1B contains four sockets for 28-pin, JEDEC compatible devices. Two are defined as the System Area and contain EPROMs holding the standard Monitor etc. The two remaining sockets are user definable and can contain EPROM or SRAM devices.
  • Page 23 PME68-1B Manual System Area Summary Start address $080000 End address $09FFFF Boundary $020000 Boot address $000000 to $000007 Access modes Byte or Word Read Only Access time See Access Speed Selection in Chapter 4 (jumper selectable) User Area The two sockets in the user area may be configured for EPROMs, containing application programs, or for SRAMs.

  • Page 24: Local I/O And Control Devices

    PME68-1B Manual Local I/O and Control Devices PME68-1B boards contain three serial I/O Interfaces (Ports 1 to 3), a Real Time Clock with a battery back-up and a Parallel Interface and Timer Module. Serial I/O The board contains three independent serial I/O channels. The clock input for both the transmit and receive baud rate of each of the three channels is selectable to one of eight baud rate clocks driven by a Motorola 14411 baud rate generator.
  • Page 25 PME68-1B Manual The terminal interface can interrupt the 68000 CPU on level 4. The interrupt vector used is auto-interrupt vector (# 28/$000070); this cannot be changed. A diagram showing the terminal interface is given below as an example to illustrate the use of the 6850 de- vice.

  • Page 26: Address Assignment Of Terminal Interface

    PME68-1B Manual Address Assignment of Terminal Interface DEVICE: 6850 ACIA (Terminal) Address Mode Description 0C0080 Status Register 0C0080 Control Register 0C0082 Receive Data Register 0C0082 Transmit Data Register ITable 2 Default Signal Assignment - Terminal/Remote Interfaces P4/P5 Input Output Signal Protective GND connected to signal GND Transmit Data (TXD) Receive Data (RXD)

  • Page 27: Address Assignment - Remote Interface

    Port 1 (connector P4) directly to a host computer. In the configuration diagram Figure 6, both the PME 68-1B and the host are set to re- ceive data from the terminal on the Transmit Data Line (TXD) and echo it via the Re- ceive Data Line (RXD) back to the terminal.

  • Page 28: Address Assignment - Host Interface

    PME68-1B Manual Fig. 7 Configuration with a Host Computer Host Terminal... Terminal PME 68-1B Table 3 lists the default signal assignment of the Host interface. This can be re-defined by the user; see Chapter 4 Address Assignment - Host Interface Address...
  • Page 29 PME68-1B Manual Fig. 8 Interfacing with a Host Computer in Transparent Mode HOST TERMINAL Tx. Data Rx. Data PME 68-1B Page 23 Issue 5...

  • Page 30: Serial I/O Interface Summary

    PME68-1B Manual Serial I/O Interface Summary Terminal Interface (Port 1 Connector P4) Start address $0C0080 End address $0C0082 Access mode Byte Only Read and Write Usable Data Bits D8 to D15 Access time 1000ns(min) 2000ns(max) Interrupt request level Interrupt handling Fixed IRQ vector (# 28) Address: $000070 Host Interface (Port 2 Connector P3)

  • Page 31: Acia Access Time

    PME68-1B Manual Serial I/O Interface Summary contd. Remote Interface (Port 3 Connector P5) Start address $0C0101 End address $0C0103 Access mode Byte Only Read and Write Usable data bits D0 to D7 Access time 1000ns(min) 2000ns(max) Interrupt request level Interrupt handling Fixed IRQ vector (# 27) Address: $00006C ACIA Access Time...

  • Page 32: Real Time Clock

    PME68-1B Manual Real Time Clock The programmable Real Time Clock can be used in conjunction with a multi-user/multi- task operating system for real time applications. It can be used as a calendar, a real time counter and for time measurement. The RTC is a 58167A device;...

  • Page 33: Rtc Interrupts

    PME68-1B Manual RTC Interrupts The RTC can be used to interrupt the on-board CPU. This feature is selected by a jumper inserted during manufacture in field B200 and LK 60 pin 2-3. The RTC interrupt can be disabled, refer to Chapter 4, RTC Interrupts for further details. The RTC interrupt request level is fixed at level 6, the highest maskable interrupt level.

  • Page 34: Parallel I/O Interface

    The Parallel Interface and Timer module (PIT 68230) is used to provide powerful asyn- chronous parallel I/O on PME 68-1B boards. The PIT provides 24 I/O lines, 4 control lines and a 24-bit timer with a 5-bit prescaler. A Centronics type interface can be configured.

  • Page 35: Pit Interrupts

    PME68-1B Manual Table 5 Parallel I/O Interface Registers Affected Address Mode By Reset Using 0E0001 Port General Control Register (PGCR) 0E0003 Port Service Request Register (PSRR) 0E0005 Port A Data Direction Register (PADDR) 0E0007 Port B Data Direction Register (PBDDR) 0E0009 Port C Data Direction Register (PCDDR) 0E000B...

  • Page 36: Centronics Type Interface

    PME68-1B Manual The PIT interrupt signal lines (PC3 + PC5) can both be linked to interrupt request level 5. Auto-interrupt vectoring is used, the fixed interrupt vector number for the PIT (level 5) is # 29. The PIT interrupt signal line PC3 can also be linked to interrupt at level 6 if the RTC interrupt is disabled.

  • Page 37: Interrupt Handling

    PME68-1B Manual Interrupt Handling The on-board CPU is able to handle 7 different prioritised interrupt request levels. Interrupt priority levels are numbered from one to seven, level seven being the highest priority. The status register contains a three bit mask which indicates the current priority of the processor.

  • Page 38: Software Abort Switch

    PME68-1B Manual Software ABORT Switch The ABORT switch on the front panel generates a non-maskable interrupt to the CPU on level 7. This interrupt uses auto-interrupt vector # 31. The switch can be used for debug purposes (refer to ‘Abort Switch’ in Chapter 5); alternatively, the switch can be used for self test if special routines are built in.
  • Page 39 PME68-1B Manual Table 7 Interrupt Acknowledge L evel Code Level 1 Not assigned Note: FC0 to FC2 are function code signals from the 68000. The vector from the interrupting device is placed onto data bits D0 to D7 and is translated by the CPU into the address of the interrupt handling routine.
  • Page 40 PME68-1B Manual Table 8 Interrupt Vector Conversion Data Bit Data Bus D0-D7 Peripheral Vector Number V0-V7 D8-D15 ignored Address Bit Translated Address Bit A0-A7 A0= 0 A1= 0 A2= V0 A3= V1 A4= V2 A5= V3 A6= V4 A7= V5 A8-A15 A8= V6 A9= V7...

  • Page 41: Vmebus Interrupt Handling

    PME68-1B Manual VMEbus Interrupt Handling All on-board interrupts have a higher priority in the internal interrupt acknowledge daisy chain than VMEbus interrupts at the same interrupt level. VMEbus interrupt signals, IRQ1 to IRQ7, can be enabled/disabled separately using jumpers. Refer to Chapter 4 for further details. Default condition is all interrupts en- abled.

  • Page 42: Vmebus Arbitration

    Pin 21 = IACKOUT* The PME 68-1B has an on-board interrupt handler which can be configured to respond to any group of request levels. Alternatively, the interrupt handler can be disabled and the 68-1B used with an external interrupt handler.

  • Page 43: Using Pme 68-1B As The System Bus Arbiter

    The VMEbus specification defines four BR levels, BR0* to BR3* and specifies that BR3* should be used by one-level Arbiters. This is the default setting of the PME 68-1B Arbiter but the user may select any other BR level if required; see Chapter 4.

  • Page 44: Bus Release Functions

    PME68-1B Manual Figure 12 Bus Grant Daisy Chain Slot n Slot 3 Slot 2 Slot 1 Pin 4 b = BG0IN* Pin 5 b = BG0OUT* Pin 6 b = BG1IN* Pin 7 b = BG1OUT* Pin 8 b = BG2IN* Pin 9 b = BG2OUT* Pin 10 b...

  • Page 45: Vmebus Interface

    The RESET switch is a toggle switch located on the front panel (Figure 2). It can be used to carry out a RESET of all devices on the PME 68-1B board: CPU, PIT, ACIA: or produce a VME SYSRESET* signal. This carries out a general RESET of all boards and devices within the system, including 68-1B RTC, and is the default condition.
  • Page 46 PME68-1B Manual Table 10 Address Modifier Codes Address Modifier Code 5 4 3 2 1 0 Function H H H H H H Standard Supervisory Block Transfer H H H H H L Standard Supervisory Program Access H H H H L H Standard Supervisory Data Access H H H H L L Reserved...

  • Page 47: Function Codes

    Error Detection and Correction Logic (EDC) if an uncorrectable error is detected. If the PME 68-1B is bus master and BERR* becomes active, the CPU aborts the current cycle and enters an error handling routine. Available time-out settings are: 2.5ms...

  • Page 48: Connectors

    PME68-1B Manual Connectors VMEbus P1 Connector Row A Row B Row C BBSY* BCLR* ACFAIL* BG0IN* BG0OUT* BG1IN* BG1OUT* BG2IN* BG2OUT* SYSCLK BG3IN* SYSFAIL* BG3OUT* BERR* DS1* BR0* SYSRESET* DS0* BR1* LWORD* WRITE* BR2* BR3* DTACK* IACK* IACKIN* SERCLK IACKOUT* SERDAT* IRQ7* IRQ6*...

  • Page 49: P2 Pin Assignments

    PME68-1B Manual P2 Pin Assignments Row A Row B Row C LK56 LK57 LK53 LK58 LK55 LK50 LK54 LK51 LK52 + 5V + 5V + 5V + 5V Note: PA0 - PA7, PB0 - PB7, PC0 - PC7, H1 - H4 are all signals from the PIT (J50) LK50(RX), 51(TX), 52(SIG GND) refer to the Remote interface LK53(TX), 54(RX), 55(SIG GND) refer to the...

  • Page 50: P3 Pin Assignments

    PME68-1B Manual P3 Pin Assignments Signal Protective GND connected to signal GND Transmit Data (TXD) Receive Data (RXD) Clear to Send (CTS) Signal GND Signal GND Data Terminal Ready (DTR) P4/P5 Pin Assignments Signal Protective GND connected to signal GND Transmit Data (TXD) Receive Data (RXD) Request to Send (RTS)

  • Page 51: Chapter 4 - Configuration

    PME68-1B Manual Chapter 4 - Configuration Preparation For Use To communicate with the board a terminal must be connected to Port 1 (connector P4). This allows the PME68/Monitor to be used for program development, up/download of programs etc. The default set-up of all RS-232C interfaces is: 8 data bits 1 stop bit No parity...
  • Page 52 The batteries should not be positioned close to other heat emitting components. (The battery on the PME 68-1B has been positioned near the edge of the board at a location well away from potentially hot components.) To measure the battery voltage it is necessary to use a meter or measuring instrument with an impedance or input impedance greater than 1M Ohm.

  • Page 53: Link Settings

    PME68-1B Manual Link Settings PME68-1B contains a number of links which enable the board to be configured to suit system requirements. Other parameters can be changed by replacing PAL devices. CAUTION: Components may be damaged by incorrectly fitted, or illegal combinations of links.
  • Page 54 PME68-1B Manual Table 12 L inks settings Applicable to All Variants contd. 1-14, 2-13, 3-12, 4-11, 5-10, 6-9, 7-8 See WB2 WB2# 1-2-WB1# 1 WC1# 1-WC2# 1, WC1# 2-WC2# 2 None or PME68/Monitor WC1# 4-WC2# 2 WC1# 1-WC2# 1,WC1# 4-WC2# 2,WC1# 2-3 PLUM Monitor WD1# 1-WD2# 1, WD1# 2-WD2# 2, WD1# 4-WD1# 2 See WD1 WF1# 1-WF2# 1&2&3...
  • Page 55 PME68-1B Manual Table 15 Standard Variant Default Settings Function Setting Links Fitted RTC Interrupt Interrupt Level 6 B200 1-2, LK60 2-3 Baud Rate Selection 9600 BR12 # 1-3, WF1# 1toWF2# 1,2&3, BERR* Enabled BR27 # 1-2, BR28# 1-2,# 3-4, WK1 # 1-2 Time-out Counter for 2.5ms BR26 # 1-2, WK1# 1-2,...
  • Page 56 PME68-1B Manual Figure 14 L ink Areas Page 50 Issue 5...
  • Page 57 PME68-1B Manual Blank Page Page 51 Issue 5...

  • Page 58: Ram/Prom/Eprom Area

    PME68-1B Manual RAM/PROM/EPROM Area System Area The board is normally supplied with two 2764 EPROM devices installed in the system area (J24 and 40) for the PME68/Monitor, or alternatively two 27256 EPROMs for PLUM. These can be replaced with other devices; wire-wrap areas WC1 and WC2 pro- vide the connections for address and control signals as detailed in Table 17.
  • Page 59 PME68-1B Manual Figure 15 L ocation of System EPROM Area Page 53 Issue 5...

  • Page 60: User Area

    PME68-1B Manual User Area The user area (J25 and 41) will accept two devices (of the same type) from those de- tailed in Table 16. Address and control lines are defined by wire-wrap areas WD1 and WD2. The standard (default) devices are a 2764/27128 EPROM. Table 18 defines the jumper field settings required for these devices.
  • Page 61 PME68-1B Manual Figure 16 L ocation of the User Area Figure 17 Jumper Fields for System/User Areas R/W* J24 and J40 JEDECS J25 and J41 Pin 26 JEDECS J24 and J40 J25 and J41 J24 and J40 Pin 26 J25 and J41 JEDECS JEDECS JEDECS...

  • Page 62: Access Speed Select

    PME68-1B Manual Access Speed Select Jumper fields BR6 and BR7 are provided to enable the access speed of the EPROM/RAM areas to be adjusted to suit the devices fitted, see Table 19. Figure 18 shows the location of BR6 and BR7. Table 19 Access Speed Selection Jumper Jumper...

  • Page 63: Local I/O And Control Devices

    PME68-1B Manual Local I/O and Control Devices Terminal Interface A hardware diagram of the interface is given in Figure 20. Default setting is defined in Chapter 3 and the default pin assignment in Table 2. Changing the baud rate is described later in the section headed Baud Rate Selection, other transmission parameters are changed using the PME 68 Monitor PF command.

  • Page 64: Remote Interface

    PME68-1B Manual Remote Interface The transmission format default settings and the method of re-selection is the same as the Terminal Interface. A hardware diagram is given in Fig. 22. The signal assignment of the pins of P5 are controlled by jumper block BR14 see Fig. 21. Default settings are as Table 2 in Chapter 3.

  • Page 65: Host Interface

    PME68-1B Manual Host Interface Port 2 (connector P3) may be used for up/down loading of user programs and data or, in the transparent mode, to interface the terminal connected to Port 1 (connector P4) di- rectly to a host computer. A diagram of the host interface is given in Figure 24 and the location of jumper block BR16 is shown below in Figure 23.

  • Page 66: Baud Rate Selection

    PME68-1B Manual Baud Rate Selection Tables 20 and 21 define the baud rate values available; Figure 26 shows the circuit dia- gram of the baud rate selection devices. Figure 25 shows the location of the baud rate selection areas. Jumper field BR12 defines the ratio of the baud rates. A jumper between pin 1 and 3 (default condition) make the baud rates listed in Table 20 available.
  • Page 67 PME68-1B Manual Figure 25 L ocation of the Baud Rate Selection Areas BR12 Figure 26 Baud Rate Selection Devices BR12 TINP1 TINP2 TINP3 14411 RESET Page 61 Issue 5...

  • Page 68: Rtc Interrupts

    PME68-1B Manual RTC Interrupts The RTC interrupt level is selectable between: RTC interrupt PIT PC3 interrupt These options are set by LK60 and B200 LK60 B200 * NOTE. PIT PC3 by default RTC only interrupts on level 6; so PIT PC3 only for this combination BR18 Pin 2-3 should be removed.

  • Page 69: Parallel I/O Interface And Timer

    PME68-1B Manual Parallel I/O Interface and Timer Centronics Type Interface The PIT can be used as a Centronics type parallel interface. This allows connection of a Centronics compatible printer with the handshake protocol under full software control. This application uses 8 input and output signals. The output signals are driven by a 74LS645-1 device with a drive capacity of 48mA.
  • Page 70 PME68-1B Manual Figure 29 PIT Signal Assignment JUMP 3 BR18 ADDRESS BUS DATA BUS 680 R8 68230 IRQPIT RESET* PA0 P2A PA1 P2A R/W* PA2 P2A DTACKBUS* PA3 P2A CSPIT* PA4 P2A PA5 P2A DTACK* PA6 P2A PA7 P2A H1 P2A H2 P2A H3 P2A H4 P2A...
  • Page 71 PME68-1B Manual Interrupt Handling ACFAIL Interrupt The position of the ACFAIL jumper field is BR20, shown on the location diagram Fig- ure 30. The pins of BR20 are connected as follows: BR20 Connected to ACFAIL* (from Receiver) IRQ6 HALT (of 68000 CPU) If a connection is made between pins 1 and 3, the on-board CPU will stop all activities immediately after the ACFAIL signal is asserted.

  • Page 72: Interrupt Handling

    PME68-1B Manual VMEbus Interrupt Handling All VMEbus interrupt signals, IRQ1 to IRQ7, can be enabled/disabled separately using jumper field WA1 to WA7, as shown in Figure 32. The position of the jumpers are shown below in Figure 31. When a jumper is inserted an incoming IRQ signal will be acknowledged by the CPU; removing a jumper disables the equivalent IRQ signal.

  • Page 73: Vmebus Arbitration

    PME68-1B Manual VMEbus Arbitration The board may be configured to use the on-board, single-level arbiter as the system arbiter, or to react correctly to off-board arbitration. On-Board DTB Slave Bus Arbitration The default slave Bus Request level is 3. Connections are made as listed in Table 21. Table 21 Slave Arbitration Default Connections Connections between: WB2 # 1...

  • Page 74: Off-Board Arbitration

    PME68-1B Manual Off-Board Arbitration In a four level bus arbitration scheme with an external arbiter, the bus request levels require the following connections: (See Figure 33 for positions of WB1, WB2, WI1# /2/3/4) BR0* BR2* WB1# 1 to WB1# 2 WI2# 3 to WI3# 1 WB1# 1 to WB1# 4 WI1# 3 to WI4# 3...

  • Page 75: Vmebus Interface

    PME68-1B Manual VMEBUS Interface SYSCLK Signal The on-board SYSCLK driver can be isolated from the VMEbus via a jumper in position BR21. Jumper Inserted SYSCLK connected to VMEbus No Jumper SYSCLK signal not connected to VMEbus Figure 36 shows the location of jumper BR21. SYSRESET* Signal Jumper field BR2 defines whether the board drives, receives, or ignores the VMEbus signal SYSRESET*.

  • Page 76: Sysfail* Signal

    SYSFAIL* Signal The VMEbus SYSFAIL* signal informs all cards that one or more cards in the system has failed. On PME 68-1B boards this input signal is directly connected to jumper field BR19. If the jumper is installed an active SYSFAIL* signal causes the on-board CPU to jump directly to the HALT state and the red HALT LED on the front panel to light.

  • Page 77: Short I/O Address Modifier Code

    PME68-1B Manual Short I/O Address Modifier Code The 64k byte range is jumper selectable within the range $100000 to $FFFFFF, as de- fined by jumper fields WH1, WH2, WH3 and WH4. For valid decoding, jumper settings are: the corresponding address signal must be high (1). the corresponding address signal must be low (0).
  • Page 78 PME68-1B Manual Table 23 Short I/O Jumper Settings Corresponding Default Jumper Positions Address Signal Setting WH1# 1 / WH3# 1 WH1# 2 / WH3# 2 WH1# 3 / WH3# 3 WH1# 4 / WH3# 4 WH2# 1 / WH4# 1 WH2# 2 / WH4# 2 WH2# 3 / WH4# 3 WH2# 4 / WH4# 4...

  • Page 79: Bus Error Function

    PME68-1B Manual Bus Error Function The internal time-out value (BERRINT) can be altered by changing the settings of jumpers BR26 and WK1/WK2. The initial timing is set by WK1/WK2, BR26 alters this value by a factor of 10. The other jumpers involved in the chain must be left in their default positions, i.e.
  • Page 80 PME68-1B Manual Figure 41 L ocation of BERR* Jumpers BR26 Page 74 Issue 5...

  • Page 81: Chapter 5 - Pme68/Monitor

    Software Capabilities The PME68/Monitor resides in on-board EPROM. This 16k byte package provides a user interface to the hardware of the PME 68-1B CPU board. The system monitor controls communication with a terminal and exercises all other elements of the system as well as providing complete debug capability and I/O control.
  • Page 82 PME68-1B Manual The PME68/Monitor has the following capabilities and features: Block fill memory - from add1 through add2 with data Block move - move from add1 through add2 to add3 Set/display breakpoint Block search - search add1 through add2 Block test of memory Data conversion Display formatted registers Dump memory to object file...

  • Page 83: General System Overview

    $0007 RESET Switch RESET is provided by Switch 1 (SW1) on the PME 68-1B front panel. Pressing this switch causes all programs or processes to terminate, resets the CPU and the parallel I/O devices, and restarts the resident firmware. The RESET switch may be used if ‘all else fails’.

  • Page 84: Vectors And Errors

    PME68-1B Manual Vectors and Errors Exception vectors are memory locations from which the processor fetches the address of a routine which will handle an exception. All exception vectors are two words in length (32 bit). See the following table: Vector Address Number(s) Space...

  • Page 85: Interrupt Level Assignment

    PME68-1B Manual Interrupt Level Assignment The PME68/Monitor has the following interrupt level vector assignments: Default Interrupt Exception Vector Levels of the VMEBus (68000 CPU) Comment Spurious Interrupt $ 60 INTR TRAP ERROR IRQ7* $ 7C AV # 7 TRAP ERROR IRQ6* $ 78 AV # 6 TRAP ERROR...

  • Page 86: Return To The Monitor

    PME68-1B Manual Return to the Monitor Return to the PME68/Monitor may be initiated via software. A useful means of doing this from a user application program is: -- User Program -- TRAP # 14 i.e. Adding a TRAP # 14 instruction at the end of the user program. The other user Trap locations, from UT0 to UT13 and UT15, are preset with the appropriate error handling routine, they can be used by application programs.

  • Page 87: Pme68/Monitor Memory Map

    $000007 $000008 System RAM $000FFF $001000 User RAM $01FFFF $020000 Reserved $080007 $080008 System EPROM $09FFFF $0A0000 User EPROM $0BFFFF $0C0000 I/O devices $100000 The memory map of the PME 68-1B is shown in Chapter 3. Page 81 Issue 5...

  • Page 88: Operation Of The Pme68/Monitor

    PME68-1B Manual Operation of the PME68/Monitor Operating Procedure Once the module has been set up and power applied, automatic CPU reset circuitry gives program control to the monitor. Once the initialisation sequence is complete the system is ready to communicate with a user terminal attached to Port 1 (connector P4) of the CPU.

  • Page 89: Terminal Control Characters

    PME68-1B Manual If a command causes the firmware to access any unused address (i.e. no memory or I/O device is located at that address), a bus trap error will occur. The contents of all CPU registers are displayed and a return to the standard input routine is performed. This also occurs if an attempt is made to write to a reserved memory area.
  • Page 90 PME68-1B Manual The command format is: > [NO] < command> < parameters> [;< options> ] < CR> RETURN key: the command is not processed until this is entered. One of the options modifying the basic command. Parameters (optional) separated from each other by a SPACE character.

  • Page 91: Monitor Commands

    PME68-1B Manual Monitor Commands Monitor commands are presented in alphabetical order, examples are used to highlight possible applications. COMMAND DESCRIPTION BF < address1> < address2> < data> Block Fill memory - from add1 through add2 with data BM < address1> < address2> < address3> Block Move - move from add1 through add2 to add3 BR[<...

  • Page 92: Block Fill Memory

    PME68-1B Manual NAME: BLOCK FILL MEMORY COMMAND SYNTAX: BF < address1> < address2> < data> < CR> FUNCTION: The BF command is used to fill a block of memory with a specified value starting at a word boundary (even address). The data value is word sized only.

  • Page 93: Get/Display Breakpoint

    PME68-1B Manual NAME: SET/DISPLAY BREAKPOINT COMMAND SYNTAX: BR[ < address> [; < count> ] ..] < CR> FUNCTION: The BR command enables portions of a user program to be executed in real-time and halted if a user-specified instruction address (breakpoint) is encountered. The breakpoint, specified within the BR command, is placed into a breakpoint table maintained by the Monitor (unless the table is whenever the Monitor gives...

  • Page 94: Block Search

    PME68-1B Manual NAME: BLOCK SEARCH COMMAND SYNTAX: BS < add1> < addr2> < data> [< mask> ][< ;option> ] < CR> BS address1 address2 ’string’ CR FUNCTION: The BS command is used to search a memory block for a specified data pattern. The data may be either a literal (ASCII) string or a number.

  • Page 95: Block Test Of Memory

    PME68-1B Manual NAME: BLOCK TEST OF MEMORY COMMAND SYNTAX: BT < address1> < address2> < CR> FUNCTION: The BT command is a destructive test of a block of memory beginning at < address1> and ending at < address2> . If this test runs without detecting errors, the memory tested will be set to zeros.

  • Page 96: Dump Memory

    PME68-1B Manual NAME: DISPLAY FORMATTED REGISTERS COMMAND SYNTAX: DF < CR> FUNCTION: The DF command displays the CPU registers of the target program. These registers are also displayed whenever the monitor regains program control (ie at breakpoints and when tracing). The instruction pointed to by the program counter is also disassembled.

  • Page 97: Go Execute Program

    PME68-1B Manual NAME: GO EXECUTE PROGRAM COMMAND SYNTAX: G[ < address> ] < CR> GO[< address> ] < CR> FUNCTION: The GO command is used to execute a program, beginning execution at a specified address. If no address is specified, execution begins at the address contained in the pseudo PC.

  • Page 98: Go Until Breakpoint

    PME68-1B Manual NAME: GO UNTIL BREAKPOINT COMMAND SYNTAX: GT< address> < CR> FUNCTION: Set a temporary breakpoint at the specified address, begin execution at the address contained in the pseudo PC. The temporary breakpoint is reset when any breakpoint is encountered. EXAMPLE: >...

  • Page 99: Help

    PME68-1B Manual NAME: HELP COMMAND SYNTAX: HE < CR> FUNCTION: The HELP command displays the monitor command names on the terminal EXAMPLE: > HE .US .SS .D2 .D3 .D4 .A5 .A2 .A3 .A4 .A5 .R2 .R3 .R4 .R5 NOBR BS GD GO GT HE MS OF...

  • Page 100: Load Object File

    PME68-1B Manual NAME: LOAD OBJECT FILE COMMAND SYNTAX: LO[n][ ; < OPTION> ] < CR> FUNCTION: The LO command enables an ASCII-converted-binary (S-records) object file to be taken from an external device and loaded into memory. Each byte of data is verified as it is loaded and if not stored correctly, an error message is displayed.

  • Page 101: Memory Display

    PME68-1B Manual NAME: MEMORY DISPLAY COMMAND SYNTAX: MD [n] < address> [ < count> ] < CR> FUNCTION: The MD command is used to display a section of memory beginning at address. The section is count bytes long, if count is not specified, it takes the value 16.

  • Page 102: Memory Modify

    PME68-1B Manual NAME MEMORY MODIFY COMMAND SYNTAX: MM[n] < address> [; < options> ] < CR> M [n] < address> [; < options> ] < CR> FUNCTION: The MM command is used to display and change memory. If a data field is specified, memory locations beginning with address are set equal to the value of the data.
  • Page 103 PME68-1B Manual MEMORY MODIFY contd. The following options are supported: Default data is byte-sized data is word-sized (two bytes) data is long word-sized (four bytes) data is byte-sized; access odd addressed bytes only data is byte-sized; access even addressed bytes only do not verify that the data stored correctly.

  • Page 104: Memory Set

    PME68-1B Manual NAME: MEMORY SET COMMAND SYNTAX: MS < address> < data> < CR> FUNCTION: The MS command is used to alter memory by setting data at the address specified. The data may be a literal (ASCII) string enclosed in apostrophes, or a number with a value no greater than a 32 bit integer.

  • Page 105: Detach Printer

    PME68-1B Manual NAME: DETACH PRINTER NOPA COMMAND SYNTAX: NOPA < CR> FUNCTION: The NOPA command is used to inhibit terminal information being ‘echoed’ on the printer. It functions as the reverse of the PA command. See also: PA NAME: OFFSET COMMAND SYNTAX: OF <...

  • Page 106: Attach Printer

    PME68-1B Manual NAME: ATTACH PRINTER COMMAND SYNTAX: PA < CR> FUNCTION: The PA command enables terminal information to be ‘echoed’ to the printer: any data displayed on the terminal will also be output to the printer. A PRINTER NOT READY message will be output if the printer is not on line or no printer is present.

  • Page 107: Transparent Mode

    PME68-1B Manual NAME: TRANSPARENT MODE COMMAND SYNTAX: TM[ < exit character> ] < CR> FUNCTION: The TM command is used to enter the transparent mode in which Port 1 and 2 are directly connected. In this mode, the terminal communicates directly with the host. Note: Both ports must be set to the same baud rate.

  • Page 108: Trace

    PME68-1B Manual NAME: TRACE COMMAND SYNTAX: TR[ < count> ] < CR> T[ < count> ] < CR> FUNCTION: The TR command executes count number of instructions beginning at the address contained in the pseudo PC. After each instruction is executed, the formatted registers are displayed on the terminal.

  • Page 109: Trace To Temporary Breakpoint

    PME68-1B Manual NAME: TRACE TO TEMPORARY BREAKPOINT COMMAND SYNTAX: TT < address> < CR> FUNCTION: The TT command executes program instructions beginning at the address contained in the pseudo PC, until address is reached or a breakpoint is encountered. EXAMPLE: > .PC 1000 >...

  • Page 110: Verify

    PME68-1B Manual NAME: VERIFY COMMAND SYNTAX: [VE[n] [ = < string> ] < CR> FUNCTION: The VE command enables the contents of memory to be compared with an ASCII-converted-binary object file read from an external device. Each byte of data from the file is compared with the content of the memory at the location into which it would be loaded.

  • Page 111: Memory Display Disassembler

    PME68-1B Manual NAME: DISPLAY/SET REGISTER .A0 - .A7 .D0 - .D7 .R0 - .R6 COMMAND SYNTAX: .< register> [ < expression> ] FUNCTION: Individual registers can be displayed and/or altered. Commands with a leading period, and the registers displayed/altered by these commands are: .A0 - .A7 address register .D0 - .D7...

  • Page 112: Memory Modify Disassembler/Assembler Mm

    PME68-1B Manual NAME: MEMORY MODIFY DISASSEMBLER/ASSEMBLER MM...;DI M ...;DI COMMAND SYNTAX: MM address ;DI < CR> FUNCTION: The Disassembler/Assembler is called as an option to the Memory Modify command. When the suffix DI is used the content of the location specified will be disassembled and a ? printed after the disassembled line.

  • Page 113: Using The Assembler/Disassembler

    PME68-1B Manual Using the Assembler/Disassembler Introduction Included in the PME68/Monitor firmware is an assembler/disassembler. This is a dy- namic assembler/editor in which the source program is not saved. Each source line is translated into the proper 68000 machine language code and is stored in memory on a line-by-line basis at the time of entry.

  • Page 114: Directives

    PME68-1B Manual Directives The assembly language can contain mnemonic directives which specify auxiliary actions to be performed by the assembler. Directives are not always translated into ma- chine language. Assembler directives assist the programmer to: control the assembler output define data and symbols allocate storage.

  • Page 115: Mnemonics And Delimiters

    PME68-1B Manual For some instructions there are two valid mnemonics for the same op-code, or there is more than one assembly language equivalent. The disassembler may choose a form different from the one originally entered. For example: BRA is returned for BT DBF is returned for DBRA The assembler recognises two forms of mnemonic for two branch instructions.

  • Page 116: Character Set

    PME68-1B Manual Character Set The character set recognised by the assembler is a subset of ASCII, and is listed below: Uppercase letters A through Z Integers 0 through 9 Arithmetic operators: + - Parentheses ( ) Characters used as special prefixes: £...
  • Page 117 PME68-1B Manual The dynamic assembler does not allow labels and comments. The specific line format looks similar to: < sp> OPERATION [OPERAND] < CR> The first < sp> is to be compatible with structured assemblers. A space must be the first character of each line.

  • Page 118: Dc.w Define Constant Directive

    ’TB’+ 1 Expression Entering and Modifying Source Programs Application programs are entered into the PME 68-1B RAM area using the one-line assembler/disassembler. It is entered in assembly language statements on a line-by-line base. The source code is not saved as it is immediately converted to machine code. This imposes several restrictions on the type of source line that can be entered.

  • Page 119: Program Input

    PME68-1B Manual Program Input A new instruction may be entered after the ? prompt. If it is a valid 68000 code, the old line is overwritten by the new entry after the < CR> . > MM 1000;DI 001000 FFFF DC.W $FFF ? MOVE.B # 1,D0 < CR> The next instruction is also displayed.

  • Page 120: Saving Programs

    The methods available will depend upon the system hardware. Upload to a Host Programs can be saved by uploading to a host computer via Port 2 of the PME 68-1B. Once a program has been sent, it can be saved on the hosts mass storage media. Up- loading to a host requires a program in the host to input the S-records from the RS232C port and save them either in RAM or directly onto the mass storage media (see para.
  • Page 121 Down-load From a Host contd. LO2 ;= DU1 2000 3000 CR The command after the equal sign is sent to the RADSTONE VME MDS and interpreted as command input. The VERIFY command should be used to ensure that data has properly loaded.

  • Page 122: User Application Software Examples

    PME68-1B Manual User Application Software Examples Several devices on the PME 68-1B CPU are free for user applications, some simple examples are given to show how these devices may be programmed. The examples are guidelines only and may be adopted for the users particular purposes. The programs be- low have been written using the PME/Ideal, ROM resident screen-oriented Edi- tor/68000 Assembler.

  • Page 123: Input Of One Line From The Remote Acia

    PME68-1B Manual Input of One Line from the Remote ACIA A string is read from the device, < CR> ($0D) terminates the input. A return to the monitor is performed at the end of the operation by a TRAP # 14 sequence. ORG $4000;...

  • Page 124: Initialisation Of The Real-Time Clock

    PME68-1B Manual Initialisation of the Real-time Clock ORG $3000; /* INITIALISE REALTIME CLOCK */ RTCLOCK : @$C0400 ;/* MM58167A BASE ADDRESS */ COUNT_1000: 1(A0) ;/* COUNTER REG OFFSETS */ COUNT_100 : 3(A0) COUNT_SECS: 5(A0) COUNT_MIN : 7(A0) COUNT_HOUR: EQU 9(A0) COUNT_DAY : 11(A0) COUNT_WEEK: EQU...

  • Page 125: Address Assignment Of I/O Devices

    PME68-1B Manual Address Assignment of I/O Devices DEVICE: J10 6850 ACIA ( Terminal ) Address: Mode: Description: 0C0080 Status Register 0C0080 Control Register 0C0082 Receive Data Register 0C0082 Transmit Data Register DEVICE: J3 6850 ACIA ( Host ) Address: Mode: Description: 0C0041 Status Register...

  • Page 126: 68230 Pi/T (Parallel Interface/Timer)

    PME68-1B Manual DEVICE: J50 68230 PIT (Parallel Interface/Timer) Affected Affected by Address Mode By Reset Read Cycle Using 0E0001 Port General Control Register (PGCR) 0E0003 Port Service Request Register (PSRR) 0E0005 Port A Data Direction Register (PADDR) 0E0007 Port B Data Direction Register (PBDDR) 0E0009 Port C Data Direction Register (PCDDR) 0E000B...

  • Page 127: 58167A Rtc (Real Time Clock)

    PME68-1B Manual DEVICE: J63 58167A RTC (Real Time Clock) (not supported by firmware) Address Mode Description 0C0401 Counter - Ten Thousands of Seconds 0C0403 Counter - Hundredths and Tenths of Seconds 0C0405 Counter - Seconds 0C0407 Counter - Minutes 0C0409 Counter - Hours 0C040B Counter - Days of Week...

  • Page 128: Error Messages And Monitor Messages

    PME68-1B Manual Error Messages and Monitor Messages Error Message Meaning PRINTER NOT READY Printer is not properly connected or cannot receive output SYNTAX ERROR Error in command line ERROR Error (prefix) ILLEGAL INSTRUCTION Instruction used an illegal op-code TRAP ERROR See Traps in MC68000 User’s Guide IS NOT A HEX DIGIT Improper character entered in a field that...

  • Page 129: Addresses Of The Main System Routines

    Note: It must be remembered that not all registers are saved automatically. Furthermore it should be noted that the use of these subroutines in an illogical sequence could affect the proper operation of the PME 68-1B CPU System Monitor. Page 123 Issue 5...

  • Page 130: S-Record Format

    PME68-1B Manual S-Record Format An S-record is a standard format used for transmitting and receiving programs and data. The whole transfer is performed in ASCII characters. There are ten possible standard S-record types, but only five are used within the PME68/Monitor environment: Header record 16-bit address Data record...
  • Page 131 PME68-1B Manual A transfer is normally performed in the following sequence: Header String of minimum 32 ASCII Nulls Header Record S1 or S2 Data Records S9 or S8 End Record S-Record Example S009000053595336384B3E 3E---------------------------------------- Checksum 00....4B----------------------------------------------------- Data, Header 09------------------------------------------------------------------------------- Byte Count S0------------------------------------------------------------------------------------- Record Type S214020000000004440002014660000CB241F8044CB1 S214020010203C0000020E428110C1538066FA487AE4...
  • Page 132 PME68-1B Manual Blank Page Page 126 Issue 5...

Table of Contents