Casio SF-7900E Service Manual & Parts List page 13

5) Main switch and power on switch
(Pin54)
When the main switch is set to on position, SW terminal of CPU receives "L", then KAC terminal will be
"L" to enable the system power on. The KI0 terminal is "H" when VDD is applied to CPU. Therefore,
when pressing the power on switch, CPU will generate a clock pulse (2 MHz) at OSCO terminal for
start up the system.
When the PDN terminal will be receiving "L" level, GATE ARRAY will send "L" signal from KON termi-
nal for cutting the line of power on switch.
6) Power supply for LCD
CPU
HD62076C03
When the system is start up, CPU will send "H" signal to VIN terminal of gate array from V2ON termi-
nal. Then, gate array will send "L" signal from VOB terminal to turn ON the transistors Q2 and Q1 for
LCD drive voltages.
(Pin36)
SW
"L"
CPU
OSCI
HD62076C03
OSCO
KAC
KIO
(Pin53)
4S66F
"H"
"L"
POWER ON SWITCH
"H"
V2ON
(Pin45) (Pin24)
VDD
MAIN SWITCH
OFF
ON
2 MHz
VDD
(Pin1)
R3
(Pin2) (Pin3)
"L"
(Pin28)
VOB
VIN
GATE ARRAY
— 11 —
from IC4
(Pin35)
PDN
GATE ARRAY
(Pin62)
SWO
"L"
KON
(Pin26)
V1~V4
C20
(Pin3)
VR1
R2
(Pin31)
GND