Sony VPL-PX41 Service Manual page 101

C (12/19) 74VHC00MTCX (IC653)
VCC 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND
C (7/19, 17/19, 19//19)
74VHC221AMTCX (IC406, IC902, IC981)
VCC 1R /C 1C 1Q 2Q 2CLR 2B 2A
D X X
16 15 14 13 12 11 10 9
CLR
Q
Q
Q
Q
CLR
1 2 3 4 5 6 7
8
1A 1B 1CLR 1Q 2Q 2C 2R /C GND
X D X
C (8/19) AD9888XS-170 (IC451)
8
R IN 0 5 2:1 8
CLAMP A/D
MUX
R IN 1 8
8
8
G IN 0 8
13 2:1
CLAMP A/D
MUX
G IN 1 17
8
8
B IN 0 20 8
2:1
CLAMP A/D
B IN 1 23 MUX
8
HSYNC0 45
2:1
2
MUX
HSYNC1 43
VSYNC0
44 2:1
MUX
VSYNC1 42
SYNC
PROCESSING
SOGIN0
12 2:1
AND
MUX
SOGIN1 16
CLOCK
REF
GENERATION
COAST 53
CLAMP 30
CKINV 29
54
CKEXT
FILT
50
VD:1,6,7,10,14,18,21,25,26,34,37,38,39
VDD:56,69,79,89,98,102,112,122
PVD:47,48,52
SCL 32
SERIAL REGISTER
GND:3,4,11,15,19,22,27,28,35,36,40,41,
AND
SDA 31
46,49,51,55,65,66,67,68,78,88,99,
POWER MANAGEMENT
A0
33
100,101,111,121,128
VPL-PX41
A B
C (14/19, 15/19, 16/19) CXA7000R-T6 (IC751, IC801, IC851)
48 47 46 45 44 43 42
49
TEST
Vref Gen.
STATUS 50
D_IN9 51
D_IN8 52
S/H S/H
D_IN7 53
D_IN6 54
S/H S/H
D_IN5 55
S/H S/H
GND 56
D/A
57
GND S/H S/H
D_IN4 58
S/H S/H
D_IN3 59
S/H S/H
D_IN2 60
D_IN1 61
D_IN0 62
MCLK 63
TG
CAL_PLS
MCLKX 64
113
DRA7-0
1 2 3 4 5 6 7
120
103
DRB7-0
110
90
DGA7-0
97
80
DGB7-0
87
C (7/19) GS1881-CTA (IC401)
70
DBA7-0
77
1
C SYNC OUT
57
DBB7-0
64
C SYNC
DATACK
123
V SLICE
125 HSOUT
VIDEO IN 2
127 VSOUT
V CLAMP
126 SOGOUT
REF
2
BYPASS
11 85
3 V CC
V SYNC OUT
9 RMIDSCV
24 BMIDSCV
VOLTAGE
REGULATOR
124 DATACKB
TIMING
GND 4
CURRENT
C
C C C C
41 40 39 38 37 36 35 34 33
VCOM_Gen.
SID_Gen.
32
PV CC
31 SH_OUT1
Line inv.
30 NC
Offset Cancel
29 SH_OUT2
Line inv.
S/H
28 NC
Offset Cancel
27 SH_OUT3
S/H
Line inv.
26 GND
Offset Cancel
S/H
25 PGND
24
S/H PGND
Line inv.
23 GND
S/H
Offset Cancel
22 SH_OUT4
S/H
Line inv.
21 NC
Offset Cancel
20 SH_OUT5
Line inv.
19 NC
Offset Cancel
18 SH_OUT6
FRP
Offset Cancel Control
17 PV
CC
8 9 10 11 12 13 14 15 16
8
7
HORIZONTAL
WINDOW D Q D Q
CIRCUIT
G Q CLK Q
NOSYNC
6
VERTICAL D Q
DETECTOR
CLK( ) Q
12V
BACK PORCH
DETECTOR
5
6-15 6-15
D E
C (12/19) ICS332-SX1738 (IC659)
V
DD
2
OTP OUTPUT
SEL 6 5 CLK2
ROM
BUFFER
WITH PLL PLL
DIVIDER
CLOCK
VALUES
SYNTHESIS
AND CONTROL
CIRCUITRY
X1/ICLK 1 CRYSTAL OUTPUT
4 CLK1
OSCILLATOR BUFFER
X2 8
3 7
GND PDTS
(BOTH OUTPUTS AND PLL)
C (7/19) M52347FP-TE (IC405)
CLAMP+ CLAMP+ HD–
TIMING V. POL H. POL OUT V OUT
CC
20 19 18 17 16 15
EDGE
CLAMP V TIME
SW
GEN GATE
LOGIC
LOGIC
H
SYNC
SEP SHAPE
1 2 3 4 5 6
H. STATE V. STATE CLAMP GREEN GND COMP/H
SW IN IN
C (12/19, 19/19) SN74LV125APWR
V CC
(IC656, IC657, IC985, IC988)
ODD/EVEN
1 OE 1
OUT
1A 2
3
R SET 1Y
2 OE 4
BACK PORCH
OUT
2A 5
2Y 6
GND 7
F G
HD+ VD+ V S/S V S/S
OUT OUT OUT IN
14 13 12 11
V. SYNC
SEP
H V V
DET SHAPE DET
7 8 9 10
COMP/H V IN V DET V TIME GATE
DET SW
14 VCC
13 4 OE
12 4A
11 4Y
10 3 OE
9
3A
8 3Y
H